diff options
| author | Jeff Ohlstein <johlstei@codeaurora.org> | 2011-06-17 13:55:38 -0700 |
|---|---|---|
| committer | David Brown <davidb@codeaurora.org> | 2011-06-17 14:54:18 -0700 |
| commit | 650f156775c2638cc02ed7df31186a09ba79666a (patch) | |
| tree | 8c8c95465a6e41412301b485b264303af119af29 | |
| parent | ebf30dc91cc8592cd72b004219cfc276b3ad2854 (diff) | |
msm: timer: compensate for timer shift in msm_read_timer_count
Some msm targets have timers whose lower bits are unreliable. So, we
present our timers as lower frequency than they actually are, and ignore
the bottom 5 bits on such targets. This compensation was erroneously
removed from the msm_read_timer_count function, so restore it.
This was broken by 94790ec25 "msm: timer: SMP timer support for msm".
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
| -rw-r--r-- | arch/arm/mach-msm/timer.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 9bfdd5ad244..2232032181b 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -102,7 +102,11 @@ static cycle_t msm_read_timer_count(struct clocksource *cs) { struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource); - return readl(clk->global_counter); + /* + * Shift timer count down by a constant due to unreliable lower bits + * on some targets. + */ + return readl(clk->global_counter) >> clk->shift; } static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt) |