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authorDavid Daney <ddaney@caviumnetworks.com>2009-08-20 12:35:53 -0700
committerRalf Baechle <ralf@linux-mips.org>2009-09-17 20:07:41 +0200
commit2608441164fde82b7fc0dd050ca0c46be0df23f8 (patch)
tree3de2da4f8598bad184d544cc7ca88711816de165
parentfff9c815291d5f4132976ac337337ea5813663e6 (diff)
MIPS: Octeon: Check all CCAs in cvmx_write_csr.
The current code only checks CCA of 0 when deciding if a dummy read is needed. Since the kernel can (and does) use other CCAs we need to mask out the CCA bits from the address. Since the address constant now fits in 16 bits, there is an added benefit that smaller code is generated. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/include/asm/octeon/cvmx.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index e31e3fe14f8..9d9381e2e3d 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -271,7 +271,7 @@ static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
* what RSL read we do, so we choose CVMX_MIO_BOOT_BIST_STAT
* because it is fast and harmless.
*/
- if ((csr_addr >> 40) == (0x800118))
+ if (((csr_addr >> 40) & 0x7ffff) == (0x118))
cvmx_read64(CVMX_MIO_BOOT_BIST_STAT);
}