diff options
| author | Mark McLoughlin <markmc@redhat.com> | 2008-11-20 15:49:46 +0000 |
|---|---|---|
| committer | Joerg Roedel <joerg.roedel@amd.com> | 2009-01-03 11:57:35 +0100 |
| commit | 622ba12a4c2148999bda9b891bfd0c6ddcb6c57e (patch) | |
| tree | 89d68fa316e9aaa23005280c2720b1aed889fa9f | |
| parent | 7a8fc25e0cc6e75fa6fdb0a856490e324218550b (diff) | |
intel-iommu: move DMA PTE defs out of dma_remapping.h
DMA_PTE_READ/WRITE are needed by kvm.
Signed-off-by: Mark McLoughlin <markmc@redhat.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| -rw-r--r-- | drivers/pci/intel-iommu.c | 22 | ||||
| -rw-r--r-- | include/linux/dma_remapping.h | 22 |
2 files changed, 22 insertions, 22 deletions
diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index 9d06f4bb6b5..26c5402b6f7 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c @@ -128,6 +128,28 @@ struct context_entry { do {(c).hi |= ((val) & ((1 << 16) - 1)) << 8;} while (0) #define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while (0) +/* + * 0: readable + * 1: writable + * 2-6: reserved + * 7: super page + * 8-11: available + * 12-63: Host physcial address + */ +struct dma_pte { + u64 val; +}; +#define dma_clear_pte(p) do {(p).val = 0;} while (0) + +#define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0) +#define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0) +#define dma_set_pte_prot(p, prot) \ + do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0) +#define dma_pte_addr(p) ((p).val & VTD_PAGE_MASK) +#define dma_set_pte_addr(p, addr) do {\ + (p).val |= ((addr) & VTD_PAGE_MASK); } while (0) +#define dma_pte_present(p) (((p).val & 3) != 0) + static void flush_unmaps_timeout(unsigned long data); DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0); diff --git a/include/linux/dma_remapping.h b/include/linux/dma_remapping.h index 9a88f7d0262..9d5874e3bec 100644 --- a/include/linux/dma_remapping.h +++ b/include/linux/dma_remapping.h @@ -11,31 +11,9 @@ struct root_entry; -/* - * 0: readable - * 1: writable - * 2-6: reserved - * 7: super page - * 8-11: available - * 12-63: Host physcial address - */ -struct dma_pte { - u64 val; -}; -#define dma_clear_pte(p) do {(p).val = 0;} while (0) - #define DMA_PTE_READ (1) #define DMA_PTE_WRITE (2) -#define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0) -#define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0) -#define dma_set_pte_prot(p, prot) \ - do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0) -#define dma_pte_addr(p) ((p).val & VTD_PAGE_MASK) -#define dma_set_pte_addr(p, addr) do {\ - (p).val |= ((addr) & VTD_PAGE_MASK); } while (0) -#define dma_pte_present(p) (((p).val & 3) != 0) - struct intel_iommu; struct dmar_domain { |