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authorDavid Daney <david.daney@cavium.com>2012-04-03 15:22:05 -0700
committerDavid Daney <david.daney@cavium.com>2012-08-31 10:46:54 -0700
commit9787c56ee376bfc3ed110c2723462361b700d7d2 (patch)
tree59b5ea2709e73b63bcc2486f6fe6d6fa2eacc8bd
parentc5aa59e88fe415b1c44d389387ec1e26450e672c (diff)
MIPS: OCTEON: Add OCTEON_IRQ_* definitions for cn68XX chips.
There are 64 workqueue, 32 watchdog, and 4 mbox. Signed-off-by: David Daney <david.daney@cavium.com>
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/irq.h7
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
index c22a3078bf1..ff0d4909d84 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -21,10 +21,11 @@ enum octeon_irq {
OCTEON_IRQ_TIMER,
/* sources in CIU_INTX_EN0 */
OCTEON_IRQ_WORKQ0,
- OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 16,
- OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15,
- OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16,
+ OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 64,
+ OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 32,
OCTEON_IRQ_MBOX1,
+ OCTEON_IRQ_MBOX2,
+ OCTEON_IRQ_MBOX3,
OCTEON_IRQ_PCI_INT0,
OCTEON_IRQ_PCI_INT1,
OCTEON_IRQ_PCI_INT2,