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authorPaulo Zanoni <paulo.r.zanoni@intel.com>2012-10-24 11:34:43 -0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-10-26 10:24:49 +0200
commitb5e508d4c01b4aab6abb90488603f9bcfbb64b52 (patch)
tree3b08f5ba3c548a42e8d234c445051883b5fbded1
parentfe2b8f9dfb05f78d525bf6668549271af1860ee5 (diff)
drm/i915: implement workaround for VTOTAL when using TRANSCODER_EDP
See the documentation for the DDI_FUNC_CTL register, EDP Input Select bits: when the EDP input selection is B, the VTOTAL_B must be programmed with the VTOTAL_EDP value, same thing for selection C. V2: Use I915_READ as suggested by Daniel Vetter. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_display.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0f3187c516c..a5be3466429 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4524,6 +4524,14 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
(adjusted_mode->crtc_vsync_start - 1) |
((adjusted_mode->crtc_vsync_end - 1) << 16));
+ /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
+ * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
+ * documented on the DDI_FUNC_CTL register description, EDP Input Select
+ * bits. */
+ if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
+ (pipe == PIPE_B || pipe == PIPE_C))
+ I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
+
/* pipesrc controls the size that is scaled from, which should
* always be the user's requested size.
*/