diff options
| author | jerin jacob <jerinjacobk@gmail.com> | 2012-10-11 22:18:51 +0530 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2012-10-18 11:45:41 +0200 |
| commit | 0cc40dac8605b3b6b099b47cdde9500d592e6583 (patch) | |
| tree | 322340d7a49068430565199ebeb18055924c7e9a | |
| parent | a12265400c18e6e67d444f05fec3a792a2f87c10 (diff) | |
MIPS: CMP: Fix physical core number calculation logic
The CPUNum Field in EBase register is 10bit wide, so after 1 bit right
shift, the mask value should be 0x1ff.
Signed-off-by: jerin jacob <jerinjacobk@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4420/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/kernel/smp-cmp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c index afc379ca375..06cd0c610f4 100644 --- a/arch/mips/kernel/smp-cmp.c +++ b/arch/mips/kernel/smp-cmp.c @@ -97,7 +97,7 @@ static void cmp_init_secondary(void) /* Enable per-cpu interrupts: platform specific */ - c->core = (read_c0_ebase() >> 1) & 0xff; + c->core = (read_c0_ebase() >> 1) & 0x1ff; #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE; #endif |