diff options
| author | Michael Chan <mchan@broadcom.com> | 2007-05-07 00:26:15 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2007-05-07 00:26:15 -0700 |
| commit | c04cb34725fdcf5fdb4135d8fdfaf6f318f10e99 (patch) | |
| tree | e4194a9f1a9914a25590dab0ca60285b29c9ac15 | |
| parent | 8ed5d97e5e0be0fb1aebad16f4c464613a0e472d (diff) | |
[TG3]: Eliminate spurious interrupts.
Spurious interrupts are often encountered especially on systems
using the 8259 PIC mode. This is because the I/O write to deassert
the interrupt is posted and won't get to the chip immediately. As
a result, the IRQ may remain asserted after the IRQ handler exits,
causing spurious interrupts.
Flush the interrupt mailbox in non-MSI handlers to de-assert the
IRQ immediately. This seems to be the most straight forward approach
after discussion with Jeff Garzik and David Miller.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/tg3.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 630c8a6c9f7..6f849bd5a7e 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -3590,8 +3590,12 @@ static irqreturn_t tg3_interrupt(int irq, void *dev_id) * Writing non-zero to intr-mbox-0 additional tells the * NIC to stop sending us irqs, engaging "in-intr-handler" * event coalescing. + * + * Flush the mailbox to de-assert the IRQ immediately to prevent + * spurious interrupts. The flush impacts performance but + * excessive spurious interrupts can be worse in some cases. */ - tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); + tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); if (tg3_irq_sync(tp)) goto out; sblk->status &= ~SD_STATUS_UPDATED; @@ -3635,8 +3639,12 @@ static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) * writing non-zero to intr-mbox-0 additional tells the * NIC to stop sending us irqs, engaging "in-intr-handler" * event coalescing. + * + * Flush the mailbox to de-assert the IRQ immediately to prevent + * spurious interrupts. The flush impacts performance but + * excessive spurious interrupts can be worse in some cases. */ - tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); + tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); if (tg3_irq_sync(tp)) goto out; if (netif_rx_schedule_prep(dev)) { |