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| author | Ben Skeggs <bskeggs@redhat.com> | 2014-02-23 23:06:22 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2014-03-26 14:00:48 +1000 |
| commit | 7a42f492a3135a2b70a28595e417a2d390a0e920 (patch) | |
| tree | 7549d33a97e014632b0348649f2110668cea0a19 | |
| parent | 61fdf6209350d6d5c5b2472c4b9e242e98ca3680 (diff) | |
drm/nve0/fifo: mask unhandled intr bits when seen, rather than all intrs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c index dbc3ff632e3..6853cd2fa6f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c @@ -743,9 +743,9 @@ nve0_fifo_intr(struct nouveau_subdev *subdev) } if (stat) { - nv_fatal(priv, "unhandled status 0x%08x\n", stat); + nv_error(priv, "INTR 0x%08x\n", stat); + nv_mask(priv, 0x002140, stat, 0x00000000); nv_wr32(priv, 0x002100, stat); - nv_wr32(priv, 0x002140, 0); } } |