diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2005-03-01 18:15:08 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 19:30:49 +0100 |
| commit | 14f18b7f7e58de9a34c4b5fd38d5f73f22fba7ac (patch) | |
| tree | dd4acaac38b4a238349fc0ef785bb84152fb1942 | |
| parent | 5068debff2dcbc8f624811e3c06d60c7c0bba744 (diff) | |
On 24K we did always disable cache parity protection - obviously not
the greatest thing to do. Try to enable parity protection, check if
we actually succeeded and print a message about the outcome of this.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/kernel/traps.c | 14 |
1 files changed, 5 insertions, 9 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index a53b1ed7b38..d06db5f8115 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -736,16 +736,12 @@ static inline void parity_protection_init(void) { switch (current_cpu_data.cputype) { case CPU_24K: - /* 24K cache parity not currently implemented in FPGA */ - printk(KERN_INFO "Disable cache parity protection for " - "MIPS 24K CPU.\n"); - write_c0_ecc(read_c0_ecc() & ~0x80000000); - break; case CPU_5KC: - /* Set the PE bit (bit 31) in the c0_ecc register. */ - printk(KERN_INFO "Enable cache parity protection for " - "MIPS 5KC/24K CPUs.\n"); - write_c0_ecc(read_c0_ecc() | 0x80000000); + write_c0_ecc(0x80000000); + back_to_back_c0_hazard(); + /* Set the PE bit (bit 31) in the c0_errctl register. */ + printk(KERN_INFO "Cache parity protection %sabled\n", + (read_c0_ecc() & 0x80000000) ? "en" : "dis"); break; case CPU_20KC: case CPU_25KF: |