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authorWill Deacon <will.deacon@arm.com>2011-08-26 16:34:51 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-08-28 10:39:53 +0100
commit0f81bb6b051ad760686b5b0fef8c731282c16ef5 (patch)
tree7af7ac41d68c1bf81a64745880645883c6e17417
parent552e0c8da8ff7099e6fe060cd7ec36ae11f5465b (diff)
ARM: 7066/1: proc-v7: disable SCTLR.TE when disabling MMU
cpu_v7_reset disables the MMU and then branches to the provided address. On Thumb-2 kernels, we should take care to clear the Thumb Exception enable bit in the System Control Register, otherwise this may wreak havok in the code to which we are branching (for example, an ARM kernel image via kexec). Reviewed-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/mm/proc-v7.S1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index a30e78542cc..dec72ee9f7a 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -66,6 +66,7 @@ ENDPROC(cpu_v7_proc_fin)
ENTRY(cpu_v7_reset)
mrc p15, 0, r1, c1, c0, 0 @ ctrl register
bic r1, r1, #0x1 @ ...............m
+ THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
mcr p15, 0, r1, c1, c0, 0 @ disable MMU
isb
mov pc, r0