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authorDaniel Vetter <daniel.vetter@ffwll.ch>2012-05-06 16:50:24 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-05-07 10:37:56 +0200
commit2e7a44814d802c8ba479164b8924070cd908d6b5 (patch)
tree60e4debfcc8e4f5737b6e2e5ccc968bfe34b6a66
parent768b107e4b3be0acf6f58e914afe4f337c00932b (diff)
drm/i915: Do no set Stencil Cache eviction LRA w/a on gen7+
I've flagged this while reviewing the first version and Ken Graunke fixed it up in v2, but unfortunately Dave Airlie picked up the wrong version. Cc: Dave Airlie <airlied@redhat.com> Cc: Kenneth Graunke <kenneth@whitecape.org> Cc: stable@kernel.org Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 80fce51e2f4..62892a826ed 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -398,10 +398,8 @@ static int init_render_ring(struct intel_ring_buffer *ring)
return ret;
}
- if (INTEL_INFO(dev)->gen >= 6) {
- I915_WRITE(INSTPM,
- INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
+ if (IS_GEN6(dev)) {
/* From the Sandybridge PRM, volume 1 part 3, page 24:
* "If this bit is set, STCunit will have LRA as replacement
* policy. [...] This bit must be reset. LRA replacement
@@ -411,6 +409,11 @@ static int init_render_ring(struct intel_ring_buffer *ring)
CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);
}
+ if (INTEL_INFO(dev)->gen >= 6) {
+ I915_WRITE(INSTPM,
+ INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
+ }
+
return ret;
}