diff options
| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-07-29 15:48:37 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-07-29 15:48:37 +0100 |
| commit | d50f58bbd979e86378dfdec982452041f0e604ef (patch) | |
| tree | 511938033b3346983175c70dd4d0afeb00b59b82 | |
| parent | 129961ecaf21c9ee899ad9067d917c1aa172fb7a (diff) | |
| parent | 79d3c2c2395a89a70d25f0c77c11afc87efab89b (diff) | |
Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into devel-stable
158 files changed, 6208 insertions, 2939 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 71cbb17ff89..21ceada460d 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -150,8 +150,8 @@ machine-$(CONFIG_ARCH_LPC32XX) := lpc32xx machine-$(CONFIG_ARCH_MMP) := mmp machine-$(CONFIG_ARCH_MSM) := msm machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 -machine-$(CONFIG_ARCH_MX1) := mx1 -machine-$(CONFIG_ARCH_MX2) := mx2 +machine-$(CONFIG_ARCH_MX1) := imx +machine-$(CONFIG_ARCH_MX2) := imx machine-$(CONFIG_ARCH_MX25) := mx25 machine-$(CONFIG_ARCH_MX3) := mx3 machine-$(CONFIG_ARCH_MX5) := mx5 diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-imx/Kconfig index 742fd4e6dcb..c5c0369bb48 100644 --- a/arch/arm/mach-mx2/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -1,42 +1,103 @@ +config IMX_HAVE_DMA_V1 + bool + +if ARCH_MX1 + +config SOC_IMX1 + select CPU_ARM920T + select IMX_HAVE_DMA_V1 + select IMX_HAVE_IOMUX_V1 + bool + +comment "MX1 platforms:" +config MACH_MXLADS + bool + +config ARCH_MX1ADS + bool "MX1ADS platform" + select MACH_MXLADS + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + help + Say Y here if you are using Motorola MX1ADS/MXLADS boards + +config MACH_SCB9328 + bool "Synertronixx scb9328" + select IMX_HAVE_PLATFORM_IMX_UART + help + Say Y here if you are using a Synertronixx scb9328 board + +endif + if ARCH_MX2 +config SOC_IMX21 + select CPU_ARM926T + select ARCH_MXC_AUDMUX_V1 + select IMX_HAVE_DMA_V1 + select IMX_HAVE_IOMUX_V1 + bool + +config SOC_IMX27 + select CPU_ARM926T + select ARCH_MXC_AUDMUX_V1 + select IMX_HAVE_DMA_V1 + select IMX_HAVE_IOMUX_V1 + bool + choice prompt "CPUs:" default MACH_MX21 config MACH_MX21 bool "i.MX21 support" - select ARCH_MXC_AUDMUX_V1 + select SOC_IMX21 help This enables support for Freescale's MX2 based i.MX21 processor. config MACH_MX27 bool "i.MX27 support" - select ARCH_MXC_AUDMUX_V1 + select SOC_IMX27 help This enables support for Freescale's MX2 based i.MX27 processor. endchoice -comment "MX2 platforms:" +endif + +if MACH_MX21 + +comment "MX21 platforms:" config MACH_MX21ADS bool "MX21ADS platform" - depends on MACH_MX21 + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND help Include support for MX21ADS platform. This includes specific configurations for the board and its peripherals. +endif + +if MACH_MX27 + +comment "MX27 platforms:" + config MACH_MX27ADS bool "MX27ADS platform" - depends on MACH_MX27 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND help Include support for MX27ADS platform. This includes specific configurations for the board and its peripherals. config MACH_PCM038 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)" - depends on MACH_MX27 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI help Include support for phyCORE-i.MX27 (aka pcm038) platform. This @@ -58,7 +119,9 @@ endchoice config MACH_CPUIMX27 bool "Eukrea CPUIMX27 module" - depends on MACH_MX27 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND help Include support for Eukrea CPUIMX27 platform. This includes specific configurations for the module and its peripherals. @@ -67,9 +130,16 @@ config MACH_EUKREA_CPUIMX27_USESDHC2 bool "CPUIMX27 integrates SDHC2 module" depends on MACH_CPUIMX27 help - This adds support for the internal SDHC2 used on CPUIMX27 used + This adds support for the internal SDHC2 used on CPUIMX27 for wifi or eMMC. +config MACH_EUKREA_CPUIMX27_USEUART4 + bool "CPUIMX27 integrates UART4 module" + depends on MACH_CPUIMX27 + help + This adds support for the internal UART4 used on CPUIMX27 + for bluetooth. + choice prompt "Baseboard" depends on MACH_CPUIMX27 @@ -78,6 +148,8 @@ choice config MACH_EUKREA_MBIMX27_BASEBOARD prompt "Eukrea MBIMX27 development board" bool + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_SPI_IMX help This adds board specific devices that can be found on Eukrea's MBIMX27 evaluation board. @@ -86,21 +158,24 @@ endchoice config MACH_MX27_3DS bool "MX27PDK platform" - depends on MACH_MX27 + select IMX_HAVE_PLATFORM_IMX_UART help Include support for MX27PDK platform. This includes specific configurations for the board and its peripherals. config MACH_IMX27LITE bool "LogicPD MX27 LITEKIT platform" - depends on MACH_MX27 + select IMX_HAVE_PLATFORM_IMX_UART help Include support for MX27 LITEKIT platform. This includes specific configurations for the board and its peripherals. config MACH_PCA100 bool "Phytec phyCARD-s (pca100)" - depends on MACH_MX27 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI help Include support for phyCARD-s (aka pca100) platform. This @@ -108,7 +183,9 @@ config MACH_PCA100 config MACH_MXT_TD60 bool "Maxtrack i-MXT TD60" - depends on MACH_MX27 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND help Include support for i-MXT (aka td60) platform. This includes specific configurations for the module and its peripherals. diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-imx/Makefile index e3254faac82..46a9fdfbbd1 100644 --- a/arch/arm/mach-mx2/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -4,14 +4,24 @@ # Object file lists. -obj-y := devices.o serial.o +obj-y := devices.o -obj-$(CONFIG_MACH_MX21) += clock_imx21.o mm-imx21.o +obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o -obj-$(CONFIG_MACH_MX27) += cpu_imx27.o -obj-$(CONFIG_MACH_MX27) += clock_imx27.o mm-imx27.o +obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o +obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o + +obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o +obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o + +# Support for CMOS sensor interface +obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o + +obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o +obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o + obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o diff --git a/arch/arm/mach-mx2/Makefile.boot b/arch/arm/mach-imx/Makefile.boot index e867398a8fd..7988a85cf07 100644 --- a/arch/arm/mach-mx2/Makefile.boot +++ b/arch/arm/mach-imx/Makefile.boot @@ -1,3 +1,7 @@ +zreladdr-$(CONFIG_ARCH_MX1) := 0x08008000 +params_phys-$(CONFIG_ARCH_MX1) := 0x08000100 +initrd_phys-$(CONFIG_ARCH_MX1) := 0x08800000 + zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000 params_phys-$(CONFIG_MACH_MX21) := 0xC0000100 initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000 diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-imx/clock-imx1.c index 6cf2d4a7511..c05096c3830 100644 --- a/arch/arm/mach-mx1/clock.c +++ b/arch/arm/mach-imx/clock-imx1.c @@ -2,18 +2,17 @@ * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix * * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. */ #include <linux/kernel.h> @@ -29,7 +28,41 @@ #include <mach/clock.h> #include <mach/hardware.h> #include <mach/common.h> -#include "crm_regs.h" + +#define IO_ADDR_CCM(off) (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off))) + +/* CCM register addresses */ +#define CCM_CSCR IO_ADDR_CCM(0x0) +#define CCM_MPCTL0 IO_ADDR_CCM(0x4) +#define CCM_SPCTL0 IO_ADDR_CCM(0xc) +#define CCM_PCDR IO_ADDR_CCM(0x20) + +#define CCM_CSCR_CLKO_OFFSET 29 +#define CCM_CSCR_CLKO_MASK (0x7 << 29) +#define CCM_CSCR_USB_OFFSET 26 +#define CCM_CSCR_USB_MASK (0x7 << 26) +#define CCM_CSCR_OSC_EN_SHIFT 17 +#define CCM_CSCR_SYSTEM_SEL (1 << 16) +#define CCM_CSCR_BCLK_OFFSET 10 +#define CCM_CSCR_BCLK_MASK (0xf << 10) +#define CCM_CSCR_PRESC (1 << 15) + +#define CCM_PCDR_PCLK3_OFFSET 16 +#define CCM_PCDR_PCLK3_MASK (0x7f << 16) +#define CCM_PCDR_PCLK2_OFFSET 4 +#define CCM_PCDR_PCLK2_MASK (0xf << 4) +#define CCM_PCDR_PCLK1_OFFSET 0 +#define CCM_PCDR_PCLK1_MASK 0xf + +#define IO_ADDR_SCM(off) (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off))) + +/* SCM register addresses */ +#define SCM_GCCR IO_ADDR_SCM(0xc) + +#define SCM_GCCR_DMA_CLK_EN_OFFSET 3 +#define SCM_GCCR_CSI_CLK_EN_OFFSET 2 +#define SCM_GCCR_MMA_CLK_EN_OFFSET 1 +#define SCM_GCCR_USBD_CLK_EN_OFFSET 0 static int _clk_enable(struct clk *clk) { @@ -596,7 +629,8 @@ int __init mx1_clocks_init(unsigned long fref) clk_enable(&hclk); clk_enable(&fclk); - mxc_timer_init(&gpt_clk, IO_ADDRESS(TIM1_BASE_ADDR), TIM1_INT); + mxc_timer_init(&gpt_clk, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), + MX1_TIM1_INT); return 0; } diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-imx/clock-imx21.c index bb419ef4d13..bb419ef4d13 100644 --- a/arch/arm/mach-mx2/clock_imx21.c +++ b/arch/arm/mach-imx/clock-imx21.c diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-imx/clock-imx27.c index 0f0823c8b17..5a1aa15c8a1 100644 --- a/arch/arm/mach-mx2/clock_imx27.c +++ b/arch/arm/mach-imx/clock-imx27.c @@ -644,7 +644,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk) _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) - _REGISTER_CLOCK(NULL, "csi", csi_clk) + _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1) _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk) diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-imx/cpu-imx27.c index d8d3b2d84dc..d8d3b2d84dc 100644 --- a/arch/arm/mach-mx2/cpu_imx27.c +++ b/arch/arm/mach-imx/cpu-imx27.c diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h new file mode 100644 index 00000000000..a8d94f07819 --- /dev/null +++ b/arch/arm/mach-imx/devices-imx1.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/mx1.h> +#include <mach/devices-common.h> + +#define imx1_add_i2c_imx(pdata) \ + imx_add_imx_i2c(0, MX1_I2C_BASE_ADDR, SZ_4K, MX1_INT_I2C, pdata) + +#define imx1_add_imx_uart0(pdata) \ + imx_add_imx_uart_3irq(0, MX1_UART1_BASE_ADDR, 0xd0, MX1_INT_UART1RX, MX1_INT_UART1TX, MX1_INT_UART1RTS, pdata) +#define imx1_add_imx_uart1(pdata) \ + imx_add_imx_uart_3irq(0, MX1_UART2_BASE_ADDR, 0xd0, MX1_INT_UART2RX, MX1_INT_UART2TX, MX1_INT_UART2RTS, pdata) diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h new file mode 100644 index 00000000000..42788e99d12 --- /dev/null +++ b/arch/arm/mach-imx/devices-imx21.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/mx21.h> +#include <mach/devices-common.h> + +#define imx21_add_i2c_imx(pdata) \ + imx_add_imx_i2c(0, MX2x_I2C_BASE_ADDR, SZ_4K, MX2x_INT_I2C, pdata) + +#define imx21_add_imx_uart0(pdata) \ + imx_add_imx_uart_1irq(0, MX21_UART1_BASE_ADDR, SZ_4K, MX21_INT_UART1, pdata) +#define imx21_add_imx_uart1(pdata) \ + imx_add_imx_uart_1irq(1, MX21_UART2_BASE_ADDR, SZ_4K, MX21_INT_UART2, pdata) +#define imx21_add_imx_uart2(pdata) \ + imx_add_imx_uart_1irq(2, MX21_UART3_BASE_ADDR, SZ_4K, MX21_INT_UART3, pdata) +#define imx21_add_imx_uart3(pdata) \ + imx_add_imx_uart_1irq(3, MX21_UART4_BASE_ADDR, SZ_4K, MX21_INT_UART4, pdata) + +#define imx21_add_mxc_nand(pdata) \ + imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata) + +#define imx21_add_spi_imx0(pdata) \ + imx_add_spi_imx(0, MX21_CSPI1_BASE_ADDR, SZ_4K, MX21_INT_CSPI1, pdata) +#define imx21_add_spi_imx1(pdata) \ + imx_add_spi_imx(1, MX21_CSPI2_BASE_ADDR, SZ_4K, MX21_INT_CSPI2, pdata) diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h new file mode 100644 index 00000000000..65e7bb7ec2e --- /dev/null +++ b/arch/arm/mach-imx/devices-imx27.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/mx27.h> +#include <mach/devices-common.h> + +#define imx27_add_i2c_imx0(pdata) \ + imx_add_imx_i2c(0, MX27_I2C1_BASE_ADDR, SZ_4K, MX27_INT_I2C1, pdata) +#define imx27_add_i2c_imx1(pdata) \ + imx_add_imx_i2c(1, MX27_I2C2_BASE_ADDR, SZ_4K, MX27_INT_I2C2, pdata) + +#define imx27_add_imx_uart0(pdata) \ + imx_add_imx_uart_1irq(0, MX27_UART1_BASE_ADDR, SZ_4K, MX27_INT_UART1, pdata) +#define imx27_add_imx_uart1(pdata) \ + imx_add_imx_uart_1irq(1, MX27_UART2_BASE_ADDR, SZ_4K, MX27_INT_UART2, pdata) +#define imx27_add_imx_uart2(pdata) \ + imx_add_imx_uart_1irq(2, MX27_UART3_BASE_ADDR, SZ_4K, MX27_INT_UART3, pdata) +#define imx27_add_imx_uart3(pdata) \ + imx_add_imx_uart_1irq(3, MX27_UART4_BASE_ADDR, SZ_4K, MX27_INT_UART4, pdata) +#define imx27_add_imx_uart4(pdata) \ + imx_add_imx_uart_1irq(4, MX27_UART5_BASE_ADDR, SZ_4K, MX27_INT_UART5, pdata) +#define imx27_add_imx_uart5(pdata) \ + imx_add_imx_uart_1irq(5, MX27_UART6_BASE_ADDR, SZ_4K, MX27_INT_UART6, pdata) + +#define imx27_add_mxc_nand(pdata) \ + imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata) + +#define imx27_add_spi_imx0(pdata) \ + imx_add_spi_imx(0, MX27_CSPI1_BASE_ADDR, SZ_4K, MX27_INT_CSPI1, pdata) +#define imx27_add_spi_imx1(pdata) \ + imx_add_spi_imx(1, MX27_CSPI2_BASE_ADDR, SZ_4K, MX27_INT_CSPI2, pdata) +#define imx27_add_spi_imx2(pdata) \ + imx_add_spi_imx(2, MX27_CSPI3_BASE_ADDR, SZ_4K, MX27_INT_CSPI3, pdata) diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-imx/devices.c index a0aeb8a4adc..9c271a752b8 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-imx/devices.c @@ -11,6 +11,9 @@ * * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * Copyright 2008 Sascha Hauer, kernel@pengutronix.de + * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> + * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -32,6 +35,7 @@ #include <linux/platform_device.h> #include <linux/gpio.h> #include <linux/dma-mapping.h> +#include <linux/serial.h> #include <mach/irqs.h> #include <mach/hardware.h> @@ -40,38 +44,179 @@ #include "devices.h" -/* - * SPI master controller - * - * - i.MX1: 2 channel (slighly different register setting) - * - i.MX21: 2 channel - * - i.MX27: 3 channel - */ -#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \ - static struct resource mxc_spi_resources ## n[] = { \ - { \ - .start = baseaddr, \ - .end = baseaddr + SZ_4K - 1, \ - .flags = IORESOURCE_MEM, \ - }, { \ - .start = irq, \ - .end = irq, \ - .flags = IORESOURCE_IRQ, \ - }, \ - }; \ - \ - struct platform_device mxc_spi_device ## n = { \ - .name = "spi_imx", \ - .id = n, \ - .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \ - .resource = mxc_spi_resources ## n, \ +#if defined(CONFIG_ARCH_MX1) +static struct resource imx1_camera_resources[] = { + { + .start = 0x00224000, + .end = 0x00224010, + .flags = IORESOURCE_MEM, + }, { + .start = MX1_CSI_INT, + .end = MX1_CSI_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 imx1_camera_dmamask = DMA_BIT_MASK(32); + +struct platform_device imx1_camera_device = { + .name = "mx1-camera", + .id = 0, /* This is used to put cameras on this interface */ + .dev = { + .dma_mask = &imx1_camera_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = imx1_camera_resources, + .num_resources = ARRAY_SIZE(imx1_camera_resources), +}; + +static struct resource imx_rtc_resources[] = { + { + .start = 0x00204000, + .end = 0x00204024, + .flags = IORESOURCE_MEM, + }, { + .start = MX1_RTC_INT, + .end = MX1_RTC_INT, + .flags = IORESOURCE_IRQ, + }, { + .start = MX1_RTC_SAMINT, + .end = MX1_RTC_SAMINT, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_rtc_device = { + .name = "rtc-imx", + .id = 0, + .resource = imx_rtc_resources, + .num_resources = ARRAY_SIZE(imx_rtc_resources), +}; + +static struct resource imx_wdt_resources[] = { + { + .start = 0x00201000, + .end = 0x00201008, + .flags = IORESOURCE_MEM, + }, { + .start = MX1_WDT_INT, + .end = MX1_WDT_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_wdt_device = { + .name = "imx-wdt", + .id = 0, + .resource = imx_wdt_resources, + .num_resources = ARRAY_SIZE(imx_wdt_resources), +}; + +static struct resource imx_usb_resources[] = { + { + .start = 0x00212000, + .end = 0x00212148, + .flags = IORESOURCE_MEM, + }, { + .start = MX1_USBD_INT0, + .end = MX1_USBD_INT0, + .flags = IORESOURCE_IRQ, + }, { + .start = MX1_USBD_INT1, + .end = MX1_USBD_INT1, + .flags = IORESOURCE_IRQ, + }, { + .start = MX1_USBD_INT2, + .end = MX1_USBD_INT2, + .flags = IORESOURCE_IRQ, + }, { + .start = MX1_USBD_INT3, + .end = MX1_USBD_INT3, + .flags = IORESOURCE_IRQ, + }, { + .start = MX1_USBD_INT4, + .end = MX1_USBD_INT4, + .flags = IORESOURCE_IRQ, + }, { + .start = MX1_USBD_INT5, + .end = MX1_USBD_INT5, + .flags = IORESOURCE_IRQ, + }, { + .start = MX1_USBD_INT6, + .end = MX1_USBD_INT6, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_usb_device = { + .name = "imx_udc", + .id = 0, + .num_resources = ARRAY_SIZE(imx_usb_resources), + .resource = imx_usb_resources, +}; + +/* GPIO port description */ +static struct mxc_gpio_port imx_gpio_ports[] = { + { + .chip.label = "gpio-0", + .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR), + .irq = MX1_GPIO_INT_PORTA, + .virtual_irq_start = MXC_GPIO_IRQ_START, + }, { + .chip.label = "gpio-1", + .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100), + .irq = MX1_GPIO_INT_PORTB, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32, + }, { + .chip.label = "gpio-2", + .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200), + .irq = MX1_GPIO_INT_PORTC, + .virtual_irq_start = MXC_GPIO_IRQ_START + 64, + }, { + .chip.label = "gpio-3", + .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300), + .irq = MX1_GPIO_INT_PORTD, + .virtual_irq_start = MXC_GPIO_IRQ_START + 96, } +}; + +int __init imx1_register_gpios(void) +{ + return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); +} +#endif -DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1); -DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2); +#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27) #ifdef CONFIG_MACH_MX27 -DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3); +static struct resource mx27_camera_resources[] = { + { + .start = MX27_CSI_BASE_ADDR, + .end = MX27_CSI_BASE_ADDR + 0x1f, + .flags = IORESOURCE_MEM, + }, { + .start = MX27_EMMA_PRP_BASE_ADDR, + .end = MX27_EMMA_PRP_BASE_ADDR + 0x1f, + .flags = IORESOURCE_MEM, + }, { + .start = MX27_INT_CSI, + .end = MX27_INT_CSI, + .flags = IORESOURCE_IRQ, + },{ + .start = MX27_INT_EMMAPRP, + .end = MX27_INT_EMMAPRP, + .flags = IORESOURCE_IRQ, + }, +}; +struct platform_device mx27_camera_device = { + .name = "mx2-camera", + .id = 0, + .num_resources = ARRAY_SIZE(mx27_camera_resources), + .resource = mx27_camera_resources, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; #endif /* @@ -140,34 +285,6 @@ struct platform_device mxc_w1_master_device = { .resource = mxc_w1_master_resources, }; -#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \ - static struct resource pfx ## _nand_resources[] = { \ - { \ - .start = baseaddr, \ - .end = baseaddr + SZ_4K - 1, \ - .flags = IORESOURCE_MEM, \ - }, { \ - .start = irq, \ - .end = irq, \ - .flags = IORESOURCE_IRQ, \ - }, \ - }; \ - \ - struct platform_device pfx ## _nand_device = { \ - .name = "mxc_nand", \ - .id = 0, \ - .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \ - .resource = pfx ## _nand_resources, \ - } - -#ifdef CONFIG_MACH_MX21 -DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC); -#endif - -#ifdef CONFIG_MACH_MX27 -DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC); -#endif - /* * lcdc: * - i.MX1: the basic controller @@ -218,32 +335,6 @@ struct platform_device mxc_fec_device = { }; #endif -#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \ - static struct resource mxc_i2c_resources ## n[] = { \ - { \ - .start = baseaddr, \ - .end = baseaddr + SZ_4K - 1, \ - .flags = IORESOURCE_MEM, \ - }, { \ - .start = irq, \ - .end = irq, \ - .flags = IORESOURCE_IRQ, \ - } \ - }; \ - \ - struct platform_device mxc_i2c_device ## n = { \ - .name = "imx-i2c", \ - .id = n, \ - .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \ - .resource = mxc_i2c_resources ## n, \ - } - -DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C); - -#ifdef CONFIG_MACH_MX27 -DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2); -#endif - static struct resource mxc_pwm_resources[] = { { .start = MX2x_PWM_BASE_ADDR, @@ -454,26 +545,21 @@ DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); #ifdef CONFIG_MACH_MX21 DEFINE_MXC_GPIO_PORTS(MX21, imx21); + +int __init imx21_register_gpios(void) +{ + return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports)); +} #endif #ifdef CONFIG_MACH_MX27 DEFINE_MXC_GPIO_PORTS(MX27, imx27); -#endif -int __init mxc_register_gpios(void) +int __init imx27_register_gpios(void) { -#ifdef CONFIG_MACH_MX21 - if (cpu_is_mx21()) - return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports)); - else -#endif -#ifdef CONFIG_MACH_MX27 - if (cpu_is_mx27()) - return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports)); - else -#endif - return 0; + return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports)); } +#endif #ifdef CONFIG_MACH_MX21 static struct resource mx21_usbhc_resources[] = { @@ -501,3 +587,23 @@ struct platform_device mx21_usbhc_device = { }; #endif +static struct resource imx_kpp_resources[] = { + { + .start = MX2x_KPP_BASE_ADDR, + .end = MX2x_KPP_BASE_ADDR + 0xf, + .flags = IORESOURCE_MEM + }, { + .start = MX2x_INT_KPP, + .end = MX2x_INT_KPP, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_kpp_device = { + .name = "imx-keypad", + .id = -1, + .num_resources = ARRAY_SIZE(imx_kpp_resources), + .resource = imx_kpp_resources, +}; + +#endif diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-imx/devices.h index 84ed5138017..efd4527506a 100644 --- a/arch/arm/mach-mx2/devices.h +++ b/arch/arm/mach-imx/devices.h @@ -1,3 +1,11 @@ +#ifdef CONFIG_ARCH_MX1 +extern struct platform_device imx1_camera_device; +extern struct platform_device imx_rtc_device; +extern struct platform_device imx_wdt_device; +extern struct platform_device imx_usb_device; +#endif + +#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27) extern struct platform_device mxc_gpt1; extern struct platform_device mxc_gpt2; #ifdef CONFIG_MACH_MX27 @@ -6,37 +14,19 @@ extern struct platform_device mxc_gpt4; extern struct platform_device mxc_gpt5; #endif extern struct platform_device mxc_wdt; -extern struct platform_device mxc_uart_device0; -extern struct platform_device mxc_uart_device1; -extern struct platform_device mxc_uart_device2; -extern struct platform_device mxc_uart_device3; -extern struct platform_device mxc_uart_device4; -extern struct platform_device mxc_uart_device5; extern struct platform_device mxc_w1_master_device; -#ifdef CONFIG_MACH_MX21 -extern struct platform_device imx21_nand_device; -#endif -#ifdef CONFIG_MACH_MX27 -extern struct platform_device imx27_nand_device; -#endif extern struct platform_device mxc_fb_device; extern struct platform_device mxc_fec_device; extern struct platform_device mxc_pwm_device; -extern struct platform_device mxc_i2c_device0; -#ifdef CONFIG_MACH_MX27 -extern struct platform_device mxc_i2c_device1; -#endif extern struct platform_device mxc_sdhc_device0; extern struct platform_device mxc_sdhc_device1; extern struct platform_device mxc_otg_udc_device; +extern struct platform_device mx27_camera_device; extern struct platform_device mxc_otg_host; extern struct platform_device mxc_usbh1; extern struct platform_device mxc_usbh2; -extern struct platform_device mxc_spi_device0; -extern struct platform_device mxc_spi_device1; -#ifdef CONFIG_MACH_MX27 -extern struct platform_device mxc_spi_device2; -#endif extern struct platform_device mx21_usbhc_device; extern struct platform_device imx_ssi_device0; extern struct platform_device imx_ssi_device1; +extern struct platform_device imx_kpp_device; +#endif diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/mach-imx/dma-v1.c index e16014b0d13..fd1d9197d06 100644 --- a/arch/arm/plat-mxc/dma-mx1-mx2.c +++ b/arch/arm/mach-imx/dma-v1.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/plat-mxc/dma-mx1-mx2.c + * linux/arch/arm/plat-mxc/dma-v1.c * * i.MX DMA registration and IRQ dispatching * @@ -34,7 +34,7 @@ #include <asm/system.h> #include <asm/irq.h> #include <mach/hardware.h> -#include <mach/dma-mx1-mx2.h> +#include <mach/dma-v1.h> #define DMA_DCR 0x00 /* Control Register */ #define DMA_DISR 0x04 /* Interrupt status Register */ diff --git a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c index f3b169d5245..4edc5f43920 100644 --- a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009 Eric Benard - eric@eukrea.com + * Copyright (C) 2009-2010 Eric Benard - eric@eukrea.com * * Based on pcm970-baseboard.c which is : * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) @@ -24,6 +24,9 @@ #include <linux/platform_device.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> +#include <linux/backlight.h> +#include <video/platform_lcd.h> +#include <linux/input/matrix_keypad.h> #include <asm/mach/arch.h> @@ -32,8 +35,11 @@ #include <mach/imxfb.h> #include <mach/hardware.h> #include <mach/mmc.h> -#include <mach/imx-uart.h> +#include <mach/spi.h> +#include <mach/ssi.h> +#include <mach/audmux.h> +#include "devices-imx27.h" #include "devices.h" static int eukrea_mbimx27_pins[] = { @@ -48,10 +54,12 @@ static int eukrea_mbimx27_pins[] = { PE10_PF_UART3_CTS, PE11_PF_UART3_RTS, /* UART4 */ +#if !defined(MACH_EUKREA_CPUIMX27_USEUART4) PB26_AF_UART4_RTS, PB28_AF_UART4_TXD, PB29_AF_UART4_CTS, PB31_AF_UART4_RXD, +#endif /* SDHC1*/ PE18_PF_SD1_D0, PE19_PF_SD1_D1, @@ -84,10 +92,29 @@ static int eukrea_mbimx27_pins[] = { PA30_PF_CONTRAST, PA31_PF_OE_ACD, /* SPI1 */ - PD28_PF_CSPI1_SS0, PD29_PF_CSPI1_SCLK, PD30_PF_CSPI1_MISO, PD31_PF_CSPI1_MOSI, + /* SSI4 */ +#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \ + || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE) + PC16_PF_SSI4_FS, + PC17_PF_SSI4_RXD | GPIO_PUEN, + PC18_PF_SSI4_TXD | GPIO_PUEN, + PC19_PF_SSI4_CLK, +#endif +}; + +static const uint32_t eukrea_mbimx27_keymap[] = { + KEY(0, 0, KEY_UP), + KEY(0, 1, KEY_DOWN), + KEY(1, 0, KEY_RIGHT), + KEY(1, 1, KEY_LEFT), +}; + +static struct matrix_keymap_data eukrea_mbimx27_keymap_data = { + .keymap = eukrea_mbimx27_keymap, + .keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap), }; static struct gpio_led gpio_leds[] = { @@ -103,12 +130,6 @@ static struct gpio_led gpio_leds[] = { .active_low = 1, .gpio = GPIO_PORTF | 19, }, - { - .name = "backlight", - .default_trigger = "backlight", - .active_low = 0, - .gpio = GPIO_PORTE | 5, - }, }; static struct gpio_led_platform_data gpio_led_info = { @@ -127,7 +148,7 @@ static struct platform_device leds_gpio = { static struct imx_fb_videomode eukrea_mbimx27_modes[] = { { .mode = { - .name = "CMO-QGVA", + .name = "CMO-QVGA", .refresh = 60, .xres = 320, .yres = 240, @@ -141,6 +162,38 @@ static struct imx_fb_videomode eukrea_mbimx27_modes[] = { }, .pcr = 0xFAD08B80, .bpp = 16, + }, { + .mode = { + .name = "DVI-VGA", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = 32000, + .hsync_len = 1, + .left_margin = 35, + .right_margin = 0, + .vsync_len = 1, + .upper_margin = 7, + .lower_margin = 0, + }, + .pcr = 0xFA208B80, + .bpp = 16, + }, { + .mode = { + .name = "DVI-SVGA", + .refresh = 60, + .xres = 800, + .yres = 600, + .pixclock = 25000, + .hsync_len = 1, + .left_margin = 35, + .right_margin = 0, + .vsync_len = 1, + .upper_margin = 7, + .lower_margin = 0, + }, + .pcr = 0xFA208B80, + .bpp = 16, }, }; @@ -153,16 +206,52 @@ static struct imx_fb_platform_data eukrea_mbimx27_fb_data = { .dmacr = 0x00040060, }; -static struct imxuart_platform_data uart_pdata[] = { - { - .flags = IMXUART_HAVE_RTSCTS, - }, - { - .flags = IMXUART_HAVE_RTSCTS, +static void eukrea_mbimx27_bl_set_intensity(int intensity) +{ + if (intensity) + gpio_direction_output(GPIO_PORTE | 5, 1); + else + gpio_direction_output(GPIO_PORTE | 5, 0); +} + +static struct generic_bl_info eukrea_mbimx27_bl_info = { + .name = "eukrea_mbimx27-bl", + .max_intensity = 0xff, + .default_intensity = 0xff, + .set_bl_intensity = eukrea_mbimx27_bl_set_intensity, +}; + +static struct platform_device eukrea_mbimx27_bl_dev = { + .name = "generic-bl", + .id = 1, + .dev = { + .platform_data = &eukrea_mbimx27_bl_info, }, }; -#if defined(CONFIG_TOUCHSCREEN_ADS7846) +static void eukrea_mbimx27_lcd_power_set(struct plat_lcd_data *pd, + unsigned int power) +{ + if (power) + gpio_direction_output(GPIO_PORTA | 25, 1); + else + gpio_direction_output(GPIO_PORTA | 25, 0); +} + +static struct plat_lcd_data eukrea_mbimx27_lcd_power_data = { + .set_power = eukrea_mbimx27_lcd_power_set, +}; + +static struct platform_device eukrea_mbimx27_lcd_powerdev = { + .name = "platform-lcd", + .dev.platform_data = &eukrea_mbimx27_lcd_power_data, +}; + +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +#if defined(CONFIG_TOUCHSCREEN_ADS7846) \ || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) #define ADS7846_PENDOWN (GPIO_PORTD | 25) @@ -173,7 +262,6 @@ static void ads7846_dev_init(void) printk(KERN_ERR "can't get ads746 pen down GPIO\n"); return; } - gpio_direction_input(ADS7846_PENDOWN); } @@ -186,7 +274,9 @@ static struct ads7846_platform_data ads7846_config __initdata = { .get_pendown_state = ads7846_get_pendown_state, .keep_vref_on = 1, }; +#endif +#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = { [0] = { .modalias = "ads7846", @@ -201,16 +291,30 @@ static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = { static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28}; -static struct spi_imx_master eukrea_mbimx27_spi_0_data = { +static const struct spi_imx_master eukrea_mbimx27_spi0_data __initconst = { .chipselect = eukrea_mbimx27_spi_cs, .num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs), }; #endif +static struct i2c_board_info eukrea_mbimx27_i2c_devices[] = { + { + I2C_BOARD_INFO("tlv320aic23", 0x1a), + }, +}; + static struct platform_device *platform_devices[] __initdata = { &leds_gpio, }; +static struct imxmmc_platform_data sdhc_pdata = { + .dat3_card_detect = 1, +}; + +struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata = { + .flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE, +}; + /* * system init for baseboard usage. Will be called by cpuimx27 init. * @@ -222,21 +326,52 @@ void __init eukrea_mbimx27_baseboard_init(void) mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins, ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27"); - mxc_register_device(&mxc_uart_device1, &uart_pdata[0]); - mxc_register_device(&mxc_uart_device2, &uart_pdata[1]); +#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \ + || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE) + /* SSI unit master I2S codec connected to SSI_PINS_4*/ + mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0, + MXC_AUDMUX_V1_PCR_SYN | + MXC_AUDMUX_V1_PCR_TFSDIR | + MXC_AUDMUX_V1_PCR_TCLKDIR | + MXC_AUDMUX_V1_PCR_RFSDIR | + MXC_AUDMUX_V1_PCR_RCLKDIR | + MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) | + MXC_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) | + MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) + ); + mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4, + MXC_AUDMUX_V1_PCR_SYN | + MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0) + ); +#endif + + imx27_add_imx_uart1(&uart_pdata); + imx27_add_imx_uart2(&uart_pdata); +#if !defined(MACH_EUKREA_CPUIMX27_USEUART4) + imx27_add_imx_uart3(&uart_pdata); +#endif mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data); - mxc_register_device(&mxc_sdhc_device0, NULL); + mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata); -#if defined(CONFIG_TOUCHSCREEN_ADS7846) + i2c_register_board_info(0, eukrea_mbimx27_i2c_devices, + ARRAY_SIZE(eukrea_mbimx27_i2c_devices)); + + mxc_register_device(&imx_ssi_device0, &eukrea_mbimx27_ssi_pdata); + +#if defined(CONFIG_TOUCHSCREEN_ADS7846) \ || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) - /* SPI and ADS7846 Touchscreen controler init */ - mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT); + /* ADS7846 Touchscreen controller init */ mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN); - mxc_register_device(&mxc_spi_device0, &eukrea_mbimx27_spi_0_data); + ads7846_dev_init(); +#endif + +#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) + /* SPI_CS0 init */ + mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT); + imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data); spi_register_board_info(eukrea_mbimx27_spi_board_info, ARRAY_SIZE(eukrea_mbimx27_spi_board_info)); - ads7846_dev_init(); #endif /* Leds configuration */ @@ -244,6 +379,14 @@ void __init eukrea_mbimx27_baseboard_init(void) mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT); /* Backlight */ mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT); + gpio_request(GPIO_PORTE | 5, "backlight"); + platform_device_register(&eukrea_mbimx27_bl_dev); + /* LCD Reset */ + mxc_gpio_mode(GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT); + gpio_request(GPIO_PORTA | 25, "lcd_enable"); + platform_device_register(&eukrea_mbimx27_lcd_powerdev); + + mxc_register_device(&imx_kpp_device, &eukrea_mbimx27_keymap_data); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } diff --git a/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h b/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h new file mode 100644 index 00000000000..df5f522da6b --- /dev/null +++ b/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h @@ -0,0 +1,10 @@ +#ifndef __MACH_DMA_MX1_MX2_H__ +#define __MACH_DMA_MX1_MX2_H__ +/* + * Don't use this header in new code, it will go away when all users are + * converted to mach/dma-v1.h + */ + +#include <mach/dma-v1.h> + +#endif /* ifndef __MACH_DMA_MX1_MX2_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/mach-imx/include/mach/dma-v1.h index 7c4870bd5a2..287431cc13e 100644 --- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h +++ b/arch/arm/mach-imx/include/mach/dma-v1.h @@ -1,5 +1,5 @@ /* - * linux/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h + * linux/arch/arm/mach-imx/include/mach/dma-v1.h * * i.MX DMA registration and IRQ dispatching * @@ -22,8 +22,10 @@ * MA 02110-1301, USA. */ -#ifndef __ASM_ARCH_MXC_DMA_H -#define __ASM_ARCH_MXC_DMA_H +#ifndef __MACH_DMA_V1_H__ +#define __MACH_DMA_V1_H__ + +#define imx_has_dma_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) #define IMX_DMA_CHANNELS 16 @@ -102,4 +104,4 @@ enum imx_dma_prio { int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio); -#endif /* _ASM_ARCH_MXC_DMA_H */ +#endif /* __MACH_DMA_V1_H__ */ diff --git a/arch/arm/mach-mx2/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c index 1f616dcaabc..575ff1ae85a 100644 --- a/arch/arm/mach-mx2/mach-cpuimx27.c +++ b/arch/arm/mach-imx/mach-cpuimx27.c @@ -26,20 +26,24 @@ #include <linux/mtd/physmap.h> #include <linux/platform_device.h> #include <linux/serial_8250.h> +#include <linux/usb/otg.h> +#include <linux/usb/ulpi.h> +#include <linux/fsl_devices.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/mach/map.h> -#include <mach/board-eukrea_cpuimx27.h> +#include <mach/eukrea-baseboards.h> #include <mach/common.h> #include <mach/hardware.h> -#include <mach/i2c.h> #include <mach/iomux-mx27.h> -#include <mach/imx-uart.h> #include <mach/mxc_nand.h> +#include <mach/mxc_ehci.h> +#include <mach/ulpi.h> +#include "devices-imx27.h" #include "devices.h" static int eukrea_cpuimx27_pins[] = { @@ -49,10 +53,12 @@ static int eukrea_cpuimx27_pins[] = { PE14_PF_UART1_CTS, PE15_PF_UART1_RTS, /* UART4 */ +#if defined(MACH_EUKREA_CPUIMX27_USEUART4) PB26_AF_UART4_RTS, PB28_AF_UART4_TXD, PB29_AF_UART4_CTS, PB31_AF_UART4_RXD, +#endif /* FEC */ PD0_AIN_FEC_TXD0, PD1_AIN_FEC_TXD1, @@ -76,19 +82,47 @@ static int eukrea_cpuimx27_pins[] = { PD17_PF_I2C_DATA, PD18_PF_I2C_CLK, /* SDHC2 */ +#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) PB4_PF_SD2_D0, PB5_PF_SD2_D1, PB6_PF_SD2_D2, PB7_PF_SD2_D3, PB8_PF_SD2_CMD, PB9_PF_SD2_CLK, +#endif #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) /* Quad UART's IRQ */ - GPIO_PORTD | 22 | GPIO_GPIO | GPIO_IN, - GPIO_PORTD | 23 | GPIO_GPIO | GPIO_IN, - GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN, - GPIO_PORTD | 30 | GPIO_GPIO | GPIO_IN, + GPIO_PORTB | 22 | GPIO_GPIO | GPIO_IN, + GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN, + GPIO_PORTB | 27 | GPIO_GPIO | GPIO_IN, + GPIO_PORTB | 30 | GPIO_GPIO | GPIO_IN, #endif + /* OTG */ + PC7_PF_USBOTG_DATA5, + PC8_PF_USBOTG_DATA6, + PC9_PF_USBOTG_DATA0, + PC10_PF_USBOTG_DATA2, + PC11_PF_USBOTG_DATA1, + PC12_PF_USBOTG_DATA4, + PC13_PF_USBOTG_DATA3, + PE0_PF_USBOTG_NXT, + PE1_PF_USBOTG_STP, + PE2_PF_USBOTG_DIR, + PE24_PF_USBOTG_CLK, + PE25_PF_USBOTG_DATA7, + /* USBH2 */ + PA0_PF_USBH2_CLK, + PA1_PF_USBH2_DIR, + PA2_PF_USBH2_DATA7, + PA3_PF_USBH2_NXT, + PA4_PF_USBH2_STP, + PD19_AF_USBH2_DATA4, + PD20_AF_USBH2_DATA3, + PD21_AF_USBH2_DATA6, + PD22_AF_USBH2_DATA0, + PD23_AF_USBH2_DATA2, + PD24_AF_USBH2_DATA1, + PD26_AF_USBH2_DATA5, }; static struct physmap_flash_data eukrea_cpuimx27_flash_data = { @@ -111,15 +145,12 @@ static struct platform_device eukrea_cpuimx27_nor_mtd_device = { .resource = &eukrea_cpuimx27_flash_resource, }; -static struct imxuart_platform_data uart_pdata[] = { - { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, }; -static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = { +static const struct mxc_nand_platform_data +cpuimx27_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, }; @@ -127,9 +158,11 @@ static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = { static struct platform_device *platform_devices[] __initdata = { &eukrea_cpuimx27_nor_mtd_device, &mxc_fec_device, + &mxc_wdt, + &mxc_w1_master_device, }; -static struct imxi2c_platform_data eukrea_cpuimx27_i2c_1_data = { +static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = { .bitrate = 100000, }; @@ -182,34 +215,83 @@ static struct platform_device serial_device = { }; #endif +#if defined(CONFIG_USB_ULPI) +static struct mxc_usbh_platform_data otg_pdata = { + .portsc = MXC_EHCI_MODE_ULPI, + .flags = MXC_EHCI_INTERFACE_DIFF_UNI, +}; + +static struct mxc_usbh_platform_data usbh2_pdata = { + .portsc = MXC_EHCI_MODE_ULPI, + .flags = MXC_EHCI_INTERFACE_DIFF_UNI, +}; +#endif + +static struct fsl_usb2_platform_data otg_device_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_ULPI, +}; + +static int otg_mode_host; + +static int __init eukrea_cpuimx27_otg_mode(char *options) +{ + if (!strcmp(options, "host")) + otg_mode_host = 1; + else if (!strcmp(options, "device")) + otg_mode_host = 0; + else + pr_info("otg_mode neither \"host\" nor \"device\". " + "Defaulting to device\n"); + return 0; +} +__setup("otg_mode=", eukrea_cpuimx27_otg_mode); + static void __init eukrea_cpuimx27_init(void) { mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins, ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27"); - mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); + imx27_add_imx_uart0(&uart_pdata); - mxc_register_device(&imx27_nand_device, - &eukrea_cpuimx27_nand_board_info); + imx27_add_mxc_nand(&cpuimx27_nand_board_info); i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices, ARRAY_SIZE(eukrea_cpuimx27_i2c_devices)); - mxc_register_device(&mxc_i2c_device0, &eukrea_cpuimx27_i2c_1_data); + imx27_add_i2c_imx1(&cpuimx27_i2c1_data); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) /* SDHC2 can be used for Wifi */ mxc_register_device(&mxc_sdhc_device1, NULL); +#endif +#if defined(MACH_EUKREA_CPUIMX27_USEUART4) /* in which case UART4 is also used for Bluetooth */ - mxc_register_device(&mxc_uart_device3, &uart_pdata[1]); + imx27_add_imx_uart3(&uart_pdata); #endif #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) platform_device_register(&serial_device); #endif +#if defined(CONFIG_USB_ULPI) + if (otg_mode_host) { + otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_otg_host, &otg_pdata); + } + + usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_usbh2, &usbh2_pdata); +#endif + if (!otg_mode_host) + mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + #ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD eukrea_mbimx27_baseboard_init(); #endif diff --git a/arch/arm/mach-mx2/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c index b5710bf18b9..22a2b5d9121 100644 --- a/arch/arm/mach-mx2/mach-imx27lite.c +++ b/arch/arm/mach-imx/mach-imx27lite.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/platform_device.h> @@ -26,10 +22,9 @@ #include <asm/mach/map.h> #include <mach/hardware.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx27.h> -#include <mach/board-mx27lite.h> +#include "devices-imx27.h" #include "devices.h" static unsigned int mx27lite_pins[] = { @@ -59,7 +54,7 @@ static unsigned int mx27lite_pins[] = { PF23_AIN_FEC_TX_EN, }; -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -71,7 +66,7 @@ static void __init mx27lite_init(void) { mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins), "imx27lite"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); + imx27_add_imx_uart0(&uart_pdata); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } diff --git a/arch/arm/mach-mx1/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c index 51f3cfd83db..77a760cfadc 100644 --- a/arch/arm/mach-mx1/mach-mx1ads.c +++ b/arch/arm/mach-imx/mach-mx1ads.c @@ -26,10 +26,10 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/i2c.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx1.h> #include <mach/irqs.h> +#include "devices-imx1.h" #include "devices.h" static int mx1ads_pins[] = { @@ -58,12 +58,12 @@ static int mx1ads_pins[] = { * UARTs platform data */ -static struct imxuart_platform_data uart_pdata[] = { - { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, +static const struct imxuart_platform_data uart0_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static const struct imxuart_platform_data uart1_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, }; /* @@ -75,8 +75,8 @@ static struct physmap_flash_data mx1ads_flash_data = { }; static struct resource flash_resource = { - .start = IMX_CS0_PHYS, - .end = IMX_CS0_PHYS + SZ_32M - 1, + .start = MX1_CS0_PHYS, + .end = MX1_CS0_PHYS + SZ_32M - 1, .flags = IORESOURCE_MEM, }; @@ -98,7 +98,7 @@ static struct pcf857x_platform_data pcf857x_data[] = { } }; -static struct imxi2c_platform_data mx1ads_i2c_data = { +static const struct imxi2c_platform_data mx1ads_i2c_data __initconst = { .bitrate = 100000, }; @@ -121,8 +121,8 @@ static void __init mx1ads_init(void) ARRAY_SIZE(mx1ads_pins), "mx1ads"); /* UART */ - mxc_register_device(&imx_uart1_device, &uart_pdata[0]); - mxc_register_device(&imx_uart2_device, &uart_pdata[1]); + imx1_add_imx_uart0(&uart0_pdata); + imx1_add_imx_uart1(&uart1_pdata); /* Physmap flash */ mxc_register_device(&flash_device, &mx1ads_flash_data); @@ -131,7 +131,7 @@ static void __init mx1ads_init(void) i2c_register_board_info(0, mx1ads_i2c_devices, ARRAY_SIZE(mx1ads_i2c_devices)); - mxc_register_device(&imx_i2c_device, &mx1ads_i2c_data); + imx1_add_i2c_imx(&mx1ads_i2c_data); } static void __init mx1ads_timer_init(void) @@ -145,8 +145,8 @@ struct sys_timer mx1ads_timer = { MACHINE_START(MX1ADS, "Freescale MX1ADS") /* Maintainer: Sascha Hauer, Pengutronix */ - .phys_io = IMX_IO_PHYS, - .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, + .phys_io = MX1_IO_BASE_ADDR, + .io_pg_offst = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc, .boot_params = MX1_PHYS_OFFSET + 0x100, .map_io = mx1_map_io, .init_irq = mx1_init_irq, @@ -155,8 +155,8 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS") MACHINE_END MACHINE_START(MXLADS, "Freescale MXLADS") - .phys_io = IMX_IO_PHYS, - .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, + .phys_io = MX1_IO_BASE_ADDR, + .io_pg_offst = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc, .boot_params = MX1_PHYS_OFFSET + 0x100, .map_io = mx1_map_io, .init_irq = mx1_init_irq, diff --git a/arch/arm/mach-mx2/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c index 113e58d7cb4..96d7f8189f3 100644 --- a/arch/arm/mach-mx2/mach-mx21ads.c +++ b/arch/arm/mach-imx/mach-mx21ads.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/platform_device.h> @@ -28,15 +24,49 @@ #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/mach/map.h> -#include <mach/imx-uart.h> #include <mach/imxfb.h> #include <mach/iomux-mx21.h> #include <mach/mxc_nand.h> #include <mach/mmc.h> -#include <mach/board-mx21ads.h> +#include "devices-imx21.h" #include "devices.h" +/* + * Memory-mapped I/O on MX21ADS base board + */ +#define MX21ADS_MMIO_BASE_ADDR 0xf5000000 +#define MX21ADS_MMIO_SIZE SZ_16M + +#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \ + (MX21ADS_MMIO_BASE_ADDR + (offset)) + +#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11) +#define MX21ADS_CS8900A_IOBASE_REG MX21ADS_REG_ADDR(0x000000) +#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000) +#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000) +#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000) + +/* MX21ADS_IO_REG bit definitions */ +#define MX21ADS_IO_SD_WP 0x0001 /* read */ +#define MX21ADS_IO_TP6 0x0001 /* write */ +#define MX21ADS_IO_SW_SEL 0x0002 /* read */ +#define MX21ADS_IO_TP7 0x0002 /* write */ +#define MX21ADS_IO_RESET_E_UART 0x0004 +#define MX21ADS_IO_RESET_BASE 0x0008 +#define MX21ADS_IO_CSI_CTL2 0x0010 +#define MX21ADS_IO_CSI_CTL1 0x0020 +#define MX21ADS_IO_CSI_CTL0 0x0040 +#define MX21ADS_IO_UART1_EN 0x0080 +#define MX21ADS_IO_UART4_EN 0x0100 +#define MX21ADS_IO_LCDON 0x0200 +#define MX21ADS_IO_IRDA_EN 0x0400 +#define MX21ADS_IO_IRDA_FIR_SEL 0x0800 +#define MX21ADS_IO_IRDA_MD0_B 0x1000 +#define MX21ADS_IO_IRDA_MD1 0x2000 +#define MX21ADS_IO_LED4_ON 0x4000 +#define MX21ADS_IO_LED3_ON 0x8000 + static unsigned int mx21ads_pins[] = { /* CS8900A */ @@ -133,14 +163,13 @@ static struct platform_device mx21ads_nor_mtd_device = { .resource = &mx21ads_flash_resource, }; -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata_rts __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; -static struct imxuart_platform_data uart_norts_pdata = { +static const struct imxuart_platform_data uart_pdata_norts __initconst = { }; - static int mx21ads_fb_init(struct platform_device *pdev) { u16 tmp; @@ -227,7 +256,8 @@ static struct imxmmc_platform_data mx21ads_sdhc_pdata = { .exit = mx21ads_sdhc_exit, }; -static struct mxc_nand_platform_data mx21ads_nand_board_info = { +static const struct mxc_nand_platform_data +mx21ads_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, }; @@ -263,12 +293,12 @@ static void __init mx21ads_board_init(void) mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins), "mx21ads"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_uart_device2, &uart_norts_pdata); - mxc_register_device(&mxc_uart_device3, &uart_pdata); + imx21_add_imx_uart0(&uart_pdata_rts); + imx21_add_imx_uart2(&uart_pdata_norts); + imx21_add_imx_uart3(&uart_pdata_rts); mxc_register_device(&mxc_fb_device, &mx21ads_fb_data); mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata); - mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info); + imx21_add_mxc_nand(&mx21ads_nand_board_info); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } diff --git a/arch/arm/mach-mx2/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index b2f4e0db3fb..e66ffaa1c26 100644 --- a/arch/arm/mach-mx2/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c @@ -12,23 +12,25 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * This machine is known as: + * - i.MX27 3-Stack Development System + * - i.MX27 Platform Development Kit (i.MX27 PDK) */ #include <linux/platform_device.h> #include <linux/gpio.h> +#include <linux/input/matrix_keypad.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <mach/hardware.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx27.h> -#include <mach/board-mx27pdk.h> +#include "devices-imx27.h" #include "devices.h" static unsigned int mx27pdk_pins[] = { @@ -58,7 +60,7 @@ static unsigned int mx27pdk_pins[] = { PF23_AIN_FEC_TX_EN, }; -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -66,12 +68,34 @@ static struct platform_device *platform_devices[] __initdata = { &mxc_fec_device, }; +/* + * Matrix keyboard + */ + +static const uint32_t mx27_3ds_keymap[] = { + KEY(0, 0, KEY_UP), + KEY(0, 1, KEY_DOWN), + KEY(1, 0, KEY_RIGHT), + KEY(1, 1, KEY_LEFT), + KEY(1, 2, KEY_ENTER), + KEY(2, 0, KEY_F6), + KEY(2, 1, KEY_F8), + KEY(2, 2, KEY_F9), + KEY(2, 3, KEY_F10), +}; + +static struct matrix_keymap_data mx27_3ds_keymap_data = { + .keymap = mx27_3ds_keymap, + .keymap_size = ARRAY_SIZE(mx27_3ds_keymap), +}; + static void __init mx27pdk_init(void) { mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins), "mx27pdk"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); + imx27_add_imx_uart0(&uart_pdata); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data); } static void __init mx27pdk_timer_init(void) diff --git a/arch/arm/mach-mx2/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c index 6ce323669e5..9c77da98a10 100644 --- a/arch/arm/mach-mx2/mach-mx27ads.c +++ b/arch/arm/mach-imx/mach-mx27ads.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/platform_device.h> @@ -32,16 +28,44 @@ #include <asm/mach/time.h> #include <asm/mach/map.h> #include <mach/gpio.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx27.h> -#include <mach/board-mx27ads.h> #include <mach/mxc_nand.h> -#include <mach/i2c.h> #include <mach/imxfb.h> #include <mach/mmc.h> +#include "devices-imx27.h" #include "devices.h" +/* + * Base address of PBC controller, CS4 + */ +#define PBC_BASE_ADDRESS 0xf4300000 +#define PBC_REG_ADDR(offset) (void __force __iomem *) \ + (PBC_BASE_ADDRESS + (offset)) + +/* When the PBC address connection is fixed in h/w, defined as 1 */ +#define PBC_ADDR_SH 0 + +/* Offsets for the PBC Controller register */ +/* + * PBC Board version register offset + */ +#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH) +/* + * PBC Board control register 1 set address. + */ +#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH) +/* + * PBC Board control register 1 clear address. + */ +#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH) + +/* PBC Board Control Register 1 bit definitions */ +#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */ + +/* to determine the correct external crystal reference */ +#define CKIH_27MHZ_BIT_SET (1 << 3) + static unsigned int mx27ads_pins[] = { /* UART0 */ PE12_PF_UART1_TXD, @@ -141,7 +165,8 @@ static unsigned int mx27ads_pins[] = { PB9_PF_SD2_CLK, }; -static struct mxc_nand_platform_data mx27ads_nand_board_info = { +static const struct mxc_nand_platform_data +mx27ads_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, }; @@ -168,7 +193,7 @@ static struct platform_device mx27ads_nor_mtd_device = { .resource = &mx27ads_flash_resource, }; -static struct imxi2c_platform_data mx27ads_i2c_data = { +static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = { .bitrate = 100000, }; @@ -263,20 +288,8 @@ static struct platform_device *platform_devices[] __initdata = { &mxc_w1_master_device, }; -static struct imxuart_platform_data uart_pdata[] = { - { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, }; static void __init mx27ads_board_init(void) @@ -284,18 +297,18 @@ static void __init mx27ads_board_init(void) mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins), "mx27ads"); - mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); - mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); - mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); - mxc_register_device(&mxc_uart_device3, &uart_pdata[3]); - mxc_register_device(&mxc_uart_device4, &uart_pdata[4]); - mxc_register_device(&mxc_uart_device5, &uart_pdata[5]); - mxc_register_device(&imx27_nand_device, &mx27ads_nand_board_info); + imx27_add_imx_uart0(&uart_pdata); + imx27_add_imx_uart1(&uart_pdata); + imx27_add_imx_uart2(&uart_pdata); + imx27_add_imx_uart3(&uart_pdata); + imx27_add_imx_uart4(&uart_pdata); + imx27_add_imx_uart5(&uart_pdata); + imx27_add_mxc_nand(&mx27ads_nand_board_info); /* only the i2c master 1 is used on this CPU card */ i2c_register_board_info(1, mx27ads_i2c_devices, ARRAY_SIZE(mx27ads_i2c_devices)); - mxc_register_device(&mxc_i2c_device1, &mx27ads_i2c_data); + imx27_add_i2c_imx1(&mx27ads_i2c1_data); mxc_register_device(&mxc_fb_device, &mx27ads_fb_data); mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata); @@ -342,4 +355,3 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS") .init_machine = mx27ads_board_init, .timer = &mx27ads_timer, MACHINE_END - diff --git a/arch/arm/mach-mx2/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c index bc385599267..a3a1e452d4c 100644 --- a/arch/arm/mach-mx2/mach-mxt_td60.c +++ b/arch/arm/mach-imx/mach-mxt_td60.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/platform_device.h> @@ -32,14 +28,13 @@ #include <asm/mach/time.h> #include <asm/mach/map.h> #include <linux/gpio.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx27.h> #include <mach/mxc_nand.h> -#include <mach/i2c.h> #include <linux/i2c/pca953x.h> #include <mach/imxfb.h> #include <mach/mmc.h> +#include "devices-imx27.h" #include "devices.h" static unsigned int mxt_td60_pins[] __initdata = { @@ -128,12 +123,13 @@ static unsigned int mxt_td60_pins[] __initdata = { PB9_PF_SD2_CLK, }; -static struct mxc_nand_platform_data mxt_td60_nand_board_info = { +static const struct mxc_nand_platform_data +mxt_td60_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, }; -static struct imxi2c_platform_data mxt_td60_i2c_data = { +static const struct imxi2c_platform_data mxt_td60_i2c0_data __initconst = { .bitrate = 100000, }; @@ -173,7 +169,7 @@ static struct i2c_board_info mxt_td60_i2c_devices[] = { }, }; -static struct imxi2c_platform_data mxt_td60_i2c2_data = { +static const struct imxi2c_platform_data mxt_td60_i2c1_data __initconst = { .bitrate = 100000, }; @@ -239,14 +235,8 @@ static struct platform_device *platform_devices[] __initdata = { &mxc_fec_device, }; -static struct imxuart_platform_data uart_pdata[] = { - { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, }; static void __init mxt_td60_board_init(void) @@ -254,10 +244,10 @@ static void __init mxt_td60_board_init(void) mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins), "MXT_TD60"); - mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); - mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); - mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); - mxc_register_device(&imx27_nand_device, &mxt_td60_nand_board_info); + imx27_add_imx_uart0(&uart_pdata); + imx27_add_imx_uart1(&uart_pdata); + imx27_add_imx_uart2(&uart_pdata); + imx27_add_mxc_nand(&mxt_td60_nand_board_info); i2c_register_board_info(0, mxt_td60_i2c_devices, ARRAY_SIZE(mxt_td60_i2c_devices)); @@ -265,8 +255,8 @@ static void __init mxt_td60_board_init(void) i2c_register_board_info(1, mxt_td60_i2c2_devices, ARRAY_SIZE(mxt_td60_i2c2_devices)); - mxc_register_device(&mxc_i2c_device0, &mxt_td60_i2c_data); - mxc_register_device(&mxc_i2c_device1, &mxt_td60_i2c2_data); + imx27_add_i2c_imx0(&mxt_td60_i2c0_data); + imx27_add_i2c_imx1(&mxt_td60_i2c1_data); mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data); mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index a87422ed4ff..6c92deaf468 100644 --- a/arch/arm/mach-mx2/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c @@ -36,12 +36,7 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/iomux-mx27.h> -#include <mach/i2c.h> #include <asm/mach/time.h> -#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) -#include <mach/spi.h> -#endif -#include <mach/imx-uart.h> #include <mach/audmux.h> #include <mach/ssi.h> #include <mach/mxc_nand.h> @@ -49,11 +44,16 @@ #include <mach/mmc.h> #include <mach/mxc_ehci.h> #include <mach/ulpi.h> +#include <mach/imxfb.h> +#include "devices-imx27.h" #include "devices.h" #define OTG_PHY_CS_GPIO (GPIO_PORTB + 23) #define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24) +#define SPI1_SS0 (GPIO_PORTD + 28) +#define SPI1_SS1 (GPIO_PORTD + 27) +#define SD2_CD (GPIO_PORTC + 29) static int pca100_pins[] = { /* UART1 */ @@ -68,6 +68,7 @@ static int pca100_pins[] = { PB7_PF_SD2_D3, PB8_PF_SD2_CMD, PB9_PF_SD2_CLK, + SD2_CD | GPIO_GPIO | GPIO_IN, /* FEC */ PD0_AIN_FEC_TXD0, PD1_AIN_FEC_TXD1, @@ -131,13 +132,42 @@ static int pca100_pins[] = { PD23_AF_USBH2_DATA2, PD24_AF_USBH2_DATA1, PD26_AF_USBH2_DATA5, + /* display */ + PA5_PF_LSCLK, + PA6_PF_LD0, + PA7_PF_LD1, + PA8_PF_LD2, + PA9_PF_LD3, + PA10_PF_LD4, + PA11_PF_LD5, + PA12_PF_LD6, + PA13_PF_LD7, + PA14_PF_LD8, + PA15_PF_LD9, + PA16_PF_LD10, + PA17_PF_LD11, + PA18_PF_LD12, + PA19_PF_LD13, + PA20_PF_LD14, + PA21_PF_LD15, + PA22_PF_LD16, + PA23_PF_LD17, + PA26_PF_PS, + PA28_PF_HSYNC, + PA29_PF_VSYNC, + PA31_PF_OE_ACD, + /* free GPIO */ + GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN, /* GPIO0_IRQ */ + GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN, /* GPIO1_IRQ */ + GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN, /* GPIO2_IRQ */ }; -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; -static struct mxc_nand_platform_data pca100_nand_board_info = { +static const struct mxc_nand_platform_data +pca100_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, }; @@ -148,7 +178,7 @@ static struct platform_device *platform_devices[] __initdata = { &mxc_wdt, }; -static struct imxi2c_platform_data pca100_i2c_1_data = { +static const struct imxi2c_platform_data pca100_i2c1_data __initconst = { .bitrate = 100000, }; @@ -189,9 +219,9 @@ static struct spi_board_info pca100_spi_board_info[] __initdata = { }, }; -static int pca100_spi_cs[] = {GPIO_PORTD + 28, GPIO_PORTD + 27}; +static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1}; -static struct spi_imx_master pca100_spi_0_data = { +static const struct spi_imx_master pca100_spi0_data __initconst = { .chipselect = pca100_spi_cs, .num_chipselect = ARRAY_SIZE(pca100_spi_cs), }; @@ -253,6 +283,7 @@ static struct imxmmc_platform_data sdhc_pdata = { .exit = pca100_sdhc2_exit, }; +#if defined(CONFIG_USB_ULPI) static int otg_phy_init(struct platform_device *pdev) { gpio_set_value(OTG_PHY_CS_GPIO, 0); @@ -276,6 +307,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = { .portsc = MXC_EHCI_MODE_ULPI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; +#endif static struct fsl_usb2_platform_data otg_device_pdata = { .operating_mode = FSL_USB2_DR_DEVICE, @@ -297,6 +329,45 @@ static int __init pca100_otg_mode(char *options) } __setup("otg_mode=", pca100_otg_mode); +/* framebuffer info */ +static struct imx_fb_videomode pca100_fb_modes[] = { + { + .mode = { + .name = "EMERGING-ETV570G0DHU", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = 39722, /* in ps (25.175 MHz) */ + .hsync_len = 30, + .left_margin = 114, + .right_margin = 16, + .vsync_len = 3, + .upper_margin = 32, + .lower_margin = 0, + }, + /* + * TFT + * Pixel pol active high + * HSYNC active low + * VSYNC active low + * use HSYNC for ACD count + * line clock disable while idle + * always enable line clock even if no data + */ + .pcr = 0xf0c08080, + .bpp = 16, + }, +}; + +static struct imx_fb_platform_data pca100_fb_data = { + .mode = pca100_fb_modes, + .num_modes = ARRAY_SIZE(pca100_fb_modes), + + .pwmr = 0x00A903FF, + .lscr1 = 0x00120300, + .dmacr = 0x00020010, +}; + static void __init pca100_init(void) { int ret; @@ -320,33 +391,24 @@ static void __init pca100_init(void) mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata); - mxc_register_device(&mxc_uart_device0, &uart_pdata); + imx27_add_imx_uart0(&uart_pdata); - mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN); mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); - mxc_register_device(&imx27_nand_device, &pca100_nand_board_info); + imx27_add_mxc_nand(&pca100_nand_board_info); /* only the i2c master 1 is used on this CPU card */ i2c_register_board_info(1, pca100_i2c_devices, ARRAY_SIZE(pca100_i2c_devices)); - mxc_register_device(&mxc_i2c_device1, &pca100_i2c_1_data); - - mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT); - mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_OUT); - - /* GPIO0_IRQ */ - mxc_gpio_mode(GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN); - /* GPIO1_IRQ */ - mxc_gpio_mode(GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN); - /* GPIO2_IRQ */ - mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN); + imx27_add_i2c_imx1(&pca100_i2c1_data); #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) + mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN); + mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN); spi_register_board_info(pca100_spi_board_info, ARRAY_SIZE(pca100_spi_board_info)); - mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data); + imx27_add_spi_imx0(&pca100_spi_0_data); #endif gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs"); @@ -372,6 +434,8 @@ static void __init pca100_init(void) mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); } + mxc_register_device(&mxc_fb_device, &pca100_fb_data); + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } diff --git a/arch/arm/mach-mx2/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index 36c89431679..9212e8f3700 100644 --- a/arch/arm/mach-mx2/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c @@ -35,14 +35,12 @@ #include <mach/board-pcm038.h> #include <mach/common.h> #include <mach/hardware.h> -#include <mach/i2c.h> #include <mach/iomux-mx27.h> -#include <mach/imx-uart.h> #include <mach/mxc_nand.h> -#include <mach/spi.h> #include <mach/mxc_ehci.h> #include <mach/ulpi.h> +#include "devices-imx27.h" #include "devices.h" static int pcm038_pins[] = { @@ -162,17 +160,12 @@ static struct platform_device pcm038_nor_mtd_device = { .resource = &pcm038_flash_resource, }; -static struct imxuart_platform_data uart_pdata[] = { - { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, { - .flags = IMXUART_HAVE_RTSCTS, - }, +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, }; -static struct mxc_nand_platform_data pcm038_nand_board_info = { +static const struct mxc_nand_platform_data +pcm038_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, }; @@ -192,7 +185,7 @@ static void __init pcm038_init_sram(void) mx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00); } -static struct imxi2c_platform_data pcm038_i2c_1_data = { +static const struct imxi2c_platform_data pcm038_i2c1_data __initconst = { .bitrate = 100000, }; @@ -215,7 +208,7 @@ static struct i2c_board_info pcm038_i2c_devices[] = { static int pcm038_spi_cs[] = {GPIO_PORTD + 28}; -static struct spi_imx_master pcm038_spi_0_data = { +static const struct spi_imx_master pcm038_spi0_data __initconst = { .chipselect = pcm038_spi_cs, .num_chipselect = ARRAY_SIZE(pcm038_spi_cs), }; @@ -305,18 +298,18 @@ static void __init pcm038_init(void) pcm038_init_sram(); - mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); - mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); - mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); + imx27_add_imx_uart0(&uart_pdata); + imx27_add_imx_uart1(&uart_pdata); + imx27_add_imx_uart2(&uart_pdata); mxc_gpio_mode(PE16_AF_OWIRE); - mxc_register_device(&imx27_nand_device, &pcm038_nand_board_info); + imx27_add_mxc_nand(&pcm038_nand_board_info); /* only the i2c master 1 is used on this CPU card */ i2c_register_board_info(1, pcm038_i2c_devices, ARRAY_SIZE(pcm038_i2c_devices)); - mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data); + imx27_add_i2c_imx1(&pcm038_i2c1_data); /* PE18 for user-LED D40 */ mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT); @@ -326,7 +319,7 @@ static void __init pcm038_init(void) /* MC13783 IRQ */ mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN); - mxc_register_device(&mxc_spi_device0, &pcm038_spi_0_data); + imx27_add_spi_imx0(&pcm038_spi0_data); spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info)); diff --git a/arch/arm/mach-mx1/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c index 7587a7a1246..88bf0d1e26e 100644 --- a/arch/arm/mach-mx1/mach-scb9328.c +++ b/arch/arm/mach-imx/mach-scb9328.c @@ -22,17 +22,17 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/irqs.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx1.h> +#include "devices-imx1.h" #include "devices.h" /* * This scb9328 has a 32MiB flash */ static struct resource flash_resource = { - .start = IMX_CS0_PHYS, - .end = IMX_CS0_PHYS + (32 * 1024 * 1024) - 1, + .start = MX1_CS0_PHYS, + .end = MX1_CS0_PHYS + (32 * 1024 * 1024) - 1, .flags = IORESOURCE_MEM, }; @@ -70,13 +70,13 @@ static struct dm9000_plat_data dm9000_platdata = { static struct resource dm9000x_resources[] = { { .name = "address area", - .start = IMX_CS5_PHYS, - .end = IMX_CS5_PHYS + 1, + .start = MX1_CS5_PHYS, + .end = MX1_CS5_PHYS + 1, .flags = IORESOURCE_MEM, /* address access */ }, { .name = "data area", - .start = IMX_CS5_PHYS + 4, - .end = IMX_CS5_PHYS + 5, + .start = MX1_CS5_PHYS + 4, + .end = MX1_CS5_PHYS + 5, .flags = IORESOURCE_MEM, /* data access */ }, { .start = IRQ_GPIOC(3), @@ -108,14 +108,13 @@ static int uart1_mxc_init(struct platform_device *pdev) ARRAY_SIZE(mxc_uart1_pins), "UART1"); } -static int uart1_mxc_exit(struct platform_device *pdev) +static void uart1_mxc_exit(struct platform_device *pdev) { mxc_gpio_release_multiple_pins(mxc_uart1_pins, ARRAY_SIZE(mxc_uart1_pins)); - return 0; } -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .init = uart1_mxc_init, .exit = uart1_mxc_exit, .flags = IMXUART_HAVE_RTSCTS, @@ -131,7 +130,7 @@ static struct platform_device *devices[] __initdata = { */ static void __init scb9328_init(void) { - mxc_register_device(&imx_uart1_device, &uart_pdata); + imx1_add_imx_uart0(&uart_pdata); printk(KERN_INFO"Scb9328: Adding devices\n"); platform_add_devices(devices, ARRAY_SIZE(devices)); diff --git a/arch/arm/mach-mx1/generic.c b/arch/arm/mach-imx/mm-imx1.c index 7f9fc1034c0..9be92b96dc8 100644 --- a/arch/arm/mach-mx1/generic.c +++ b/arch/arm/mach-imx/mm-imx1.c @@ -3,7 +3,7 @@ * Created: april 20th, 2004 * Copyright: Synertronixx GmbH * - * Common code for i.MX machines + * Common code for i.MX1 machines * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,11 +14,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * */ #include <linux/kernel.h> #include <linux/init.h> @@ -31,23 +26,25 @@ static struct map_desc imx_io_desc[] __initdata = { { - .virtual = IMX_IO_BASE, - .pfn = __phys_to_pfn(IMX_IO_PHYS), - .length = IMX_IO_SIZE, - .type = MT_DEVICE + .virtual = MX1_IO_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX1_IO_BASE_ADDR), + .length = MX1_IO_SIZE, + .type = MT_DEVICE } }; void __init mx1_map_io(void) { mxc_set_cpu_type(MXC_CPU_MX1); - mxc_arch_reset_init(IO_ADDRESS(WDT_BASE_ADDR)); + mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR)); iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc)); } +int imx1_register_gpios(void); + void __init mx1_init_irq(void) { - mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR)); + mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR)); + imx1_register_gpios(); } - diff --git a/arch/arm/mach-mx2/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c index 64134314d01..12faeeaa0a9 100644 --- a/arch/arm/mach-mx2/mm-imx21.c +++ b/arch/arm/mach-imx/mm-imx21.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-mx2/mm-imx21.c + * arch/arm/mach-imx/mm-imx21.c * * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) * @@ -77,7 +77,10 @@ void __init mx21_map_io(void) iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc)); } +int imx21_register_gpios(void); + void __init mx21_init_irq(void) { mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR)); + imx21_register_gpios(); } diff --git a/arch/arm/mach-mx2/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c index 3366ed44cfd..a24622957ff 100644 --- a/arch/arm/mach-mx2/mm-imx27.c +++ b/arch/arm/mach-imx/mm-imx27.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-mx2/mm-imx27.c + * arch/arm/mach-imx/mm-imx27.c * * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) * @@ -77,7 +77,10 @@ void __init mx27_map_io(void) iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc)); } +int imx27_register_gpios(void); + void __init mx27_init_irq(void) { mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR)); + imx27_register_gpios(); } diff --git a/arch/arm/mach-mx1/ksym_mx1.c b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c index b09ee12a4ff..b09ee12a4ff 100644 --- a/arch/arm/mach-mx1/ksym_mx1.c +++ b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c diff --git a/arch/arm/mach-mx1/mx1_camera_fiq.S b/arch/arm/mach-imx/mx1-camera-fiq.S index 9c69aa65bf1..9c69aa65bf1 100644 --- a/arch/arm/mach-mx1/mx1_camera_fiq.S +++ b/arch/arm/mach-imx/mx1-camera-fiq.S diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c index f490a406d57..f490a406d57 100644 --- a/arch/arm/mach-mx2/pcm970-baseboard.c +++ b/arch/arm/mach-imx/pcm970-baseboard.c diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c new file mode 100644 index 00000000000..afc17ce0bb5 --- /dev/null +++ b/arch/arm/mach-imx/pm-imx27.c @@ -0,0 +1,46 @@ +/* + * i.MX27 Power Management Routines + * + * Based on Freescale's BSP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License. + */ + +#include <linux/kernel.h> +#include <linux/suspend.h> +#include <linux/io.h> +#include <mach/system.h> +#include <mach/mx27.h> + +static int mx27_suspend_enter(suspend_state_t state) +{ + u32 cscr; + switch (state) { + case PM_SUSPEND_MEM: + /* Clear MPEN and SPEN to disable MPLL/SPLL */ + cscr = __raw_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); + cscr &= 0xFFFFFFFC; + __raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); + /* Executes WFI */ + arch_idle(); + break; + + default: + return -EINVAL; + } + return 0; +} + +static struct platform_suspend_ops mx27_suspend_ops = { + .enter = mx27_suspend_enter, + .valid = suspend_valid_only_mem, +}; + +static int __init mx27_pm_init(void) +{ + suspend_set_ops(&mx27_suspend_ops); + return 0; +} + +device_initcall(mx27_pm_init); diff --git a/arch/arm/mach-mx1/Kconfig b/arch/arm/mach-mx1/Kconfig deleted file mode 100644 index eb7660f5d4b..00000000000 --- a/arch/arm/mach-mx1/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -if ARCH_MX1 - -comment "MX1 platforms:" - -config MACH_MXLADS - bool - -config ARCH_MX1ADS - bool "MX1ADS platform" - select MACH_MXLADS - help - Say Y here if you are using Motorola MX1ADS/MXLADS boards - -config MACH_SCB9328 - bool "Synertronixx scb9328" - help - Say Y here if you are using a Synertronixx scb9328 board - -endif diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile deleted file mode 100644 index fc2ddf82441..00000000000 --- a/arch/arm/mach-mx1/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# Object file lists. - -EXTRA_CFLAGS += -DIMX_NEEDS_DEPRECATED_SYMBOLS -obj-y += generic.o clock.o devices.o - -# Support for CMOS sensor interface -obj-$(CONFIG_MX1_VIDEO) += ksym_mx1.o mx1_camera_fiq.o - -# Specific board support -obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o -obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o diff --git a/arch/arm/mach-mx1/Makefile.boot b/arch/arm/mach-mx1/Makefile.boot deleted file mode 100644 index 8ed1492288a..00000000000 --- a/arch/arm/mach-mx1/Makefile.boot +++ /dev/null @@ -1,4 +0,0 @@ - zreladdr-y := 0x08008000 -params_phys-y := 0x08000100 -initrd_phys-y := 0x08800000 - diff --git a/arch/arm/mach-mx1/crm_regs.h b/arch/arm/mach-mx1/crm_regs.h deleted file mode 100644 index 22e866ff0c0..00000000000 --- a/arch/arm/mach-mx1/crm_regs.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> - * - * This file may be distributed under the terms of the GNU General - * Public License, version 2. - */ - -#ifndef __ARCH_ARM_MACH_MX1_CRM_REGS_H__ -#define __ARCH_ARM_MACH_MX1_CRM_REGS_H__ - -#define CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) -#define SCM_BASE IO_ADDRESS(SCM_BASE_ADDR) - -/* CCM register addresses */ -#define CCM_CSCR (CCM_BASE + 0x0) -#define CCM_MPCTL0 (CCM_BASE + 0x4) -#define CCM_MPCTL1 (CCM_BASE + 0x8) -#define CCM_SPCTL0 (CCM_BASE + 0xC) -#define CCM_SPCTL1 (CCM_BASE + 0x10) -#define CCM_PCDR (CCM_BASE + 0x20) - -#define CCM_CSCR_CLKO_OFFSET 29 -#define CCM_CSCR_CLKO_MASK (0x7 << 29) -#define CCM_CSCR_USB_OFFSET 26 -#define CCM_CSCR_USB_MASK (0x7 << 26) -#define CCM_CSCR_SPLL_RESTART (1 << 22) -#define CCM_CSCR_MPLL_RESTART (1 << 21) -#define CCM_CSCR_OSC_EN_SHIFT 17 -#define CCM_CSCR_SYSTEM_SEL (1 << 16) -#define CCM_CSCR_BCLK_OFFSET 10 -#define CCM_CSCR_BCLK_MASK (0xF << 10) -#define CCM_CSCR_PRESC (1 << 15) -#define CCM_CSCR_SPEN (1 << 1) -#define CCM_CSCR_MPEN (1 << 0) - -#define CCM_PCDR_PCLK3_OFFSET 16 -#define CCM_PCDR_PCLK3_MASK (0x7F << 16) -#define CCM_PCDR_PCLK2_OFFSET 4 -#define CCM_PCDR_PCLK2_MASK (0xF << 4) -#define CCM_PCDR_PCLK1_OFFSET 0 -#define CCM_PCDR_PCLK1_MASK 0xF - -/* SCM register addresses */ -#define SCM_SIDR (SCM_BASE + 0x0) -#define SCM_FMCR (SCM_BASE + 0x4) -#define SCM_GPCR (SCM_BASE + 0x8) -#define SCM_GCCR (SCM_BASE + 0xC) - -#define SCM_GCCR_DMA_CLK_EN_OFFSET 3 -#define SCM_GCCR_CSI_CLK_EN_OFFSET 2 -#define SCM_GCCR_MMA_CLK_EN_OFFSET 1 -#define SCM_GCCR_USBD_CLK_EN_OFFSET 0 - -#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */ diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c deleted file mode 100644 index b6be29d1cb0..00000000000 --- a/arch/arm/mach-mx1/devices.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Sascha Hauer, kernel@pengutronix.de - * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> - * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <mach/irqs.h> -#include <mach/hardware.h> - -#include "devices.h" - -static struct resource imx_csi_resources[] = { - { - .start = 0x00224000, - .end = 0x00224010, - .flags = IORESOURCE_MEM, - }, { - .start = CSI_INT, - .end = CSI_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 imx_csi_dmamask = 0xffffffffUL; - -struct platform_device imx_csi_device = { - .name = "mx1-camera", - .id = 0, /* This is used to put cameras on this interface */ - .dev = { - .dma_mask = &imx_csi_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .resource = imx_csi_resources, - .num_resources = ARRAY_SIZE(imx_csi_resources), -}; - -static struct resource imx_i2c_resources[] = { - { - .start = 0x00217000, - .end = 0x00217010, - .flags = IORESOURCE_MEM, - }, { - .start = I2C_INT, - .end = I2C_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_i2c_device = { - .name = "imx-i2c", - .id = 0, - .resource = imx_i2c_resources, - .num_resources = ARRAY_SIZE(imx_i2c_resources), -}; - -static struct resource imx_uart1_resources[] = { - { - .start = UART1_BASE_ADDR, - .end = UART1_BASE_ADDR + 0xD0, - .flags = IORESOURCE_MEM, - }, { - .start = UART1_MINT_RX, - .end = UART1_MINT_RX, - .flags = IORESOURCE_IRQ, - }, { - .start = UART1_MINT_TX, - .end = UART1_MINT_TX, - .flags = IORESOURCE_IRQ, - }, { - .start = UART1_MINT_RTS, - .end = UART1_MINT_RTS, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_uart1_device = { - .name = "imx-uart", - .id = 0, - .num_resources = ARRAY_SIZE(imx_uart1_resources), - .resource = imx_uart1_resources, -}; - -static struct resource imx_uart2_resources[] = { - { - .start = UART2_BASE_ADDR, - .end = UART2_BASE_ADDR + 0xD0, - .flags = IORESOURCE_MEM, - }, { - .start = UART2_MINT_RX, - .end = UART2_MINT_RX, - .flags = IORESOURCE_IRQ, - }, { - .start = UART2_MINT_TX, - .end = UART2_MINT_TX, - .flags = IORESOURCE_IRQ, - }, { - .start = UART2_MINT_RTS, - .end = UART2_MINT_RTS, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_uart2_device = { - .name = "imx-uart", - .id = 1, - .num_resources = ARRAY_SIZE(imx_uart2_resources), - .resource = imx_uart2_resources, -}; - -static struct resource imx_rtc_resources[] = { - { - .start = 0x00204000, - .end = 0x00204024, - .flags = IORESOURCE_MEM, - }, { - .start = RTC_INT, - .end = RTC_INT, - .flags = IORESOURCE_IRQ, - }, { - .start = RTC_SAMINT, - .end = RTC_SAMINT, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_rtc_device = { - .name = "rtc-imx", - .id = 0, - .resource = imx_rtc_resources, - .num_resources = ARRAY_SIZE(imx_rtc_resources), -}; - -static struct resource imx_wdt_resources[] = { - { - .start = 0x00201000, - .end = 0x00201008, - .flags = IORESOURCE_MEM, - }, { - .start = WDT_INT, - .end = WDT_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_wdt_device = { - .name = "imx-wdt", - .id = 0, - .resource = imx_wdt_resources, - .num_resources = ARRAY_SIZE(imx_wdt_resources), -}; - -static struct resource imx_usb_resources[] = { - { - .start = 0x00212000, - .end = 0x00212148, - .flags = IORESOURCE_MEM, - }, { - .start = USBD_INT0, - .end = USBD_INT0, - .flags = IORESOURCE_IRQ, - }, { - .start = USBD_INT1, - .end = USBD_INT1, - .flags = IORESOURCE_IRQ, - }, { - .start = USBD_INT2, - .end = USBD_INT2, - .flags = IORESOURCE_IRQ, - }, { - .start = USBD_INT3, - .end = USBD_INT3, - .flags = IORESOURCE_IRQ, - }, { - .start = USBD_INT4, - .end = USBD_INT4, - .flags = IORESOURCE_IRQ, - }, { - .start = USBD_INT5, - .end = USBD_INT5, - .flags = IORESOURCE_IRQ, - }, { - .start = USBD_INT6, - .end = USBD_INT6, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_usb_device = { - .name = "imx_udc", - .id = 0, - .num_resources = ARRAY_SIZE(imx_usb_resources), - .resource = imx_usb_resources, -}; - -/* GPIO port description */ -static struct mxc_gpio_port imx_gpio_ports[] = { - { - .chip.label = "gpio-0", - .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR), - .irq = GPIO_INT_PORTA, - .virtual_irq_start = MXC_GPIO_IRQ_START, - }, { - .chip.label = "gpio-1", - .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100), - .irq = GPIO_INT_PORTB, - .virtual_irq_start = MXC_GPIO_IRQ_START + 32, - }, { - .chip.label = "gpio-2", - .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200), - .irq = GPIO_INT_PORTC, - .virtual_irq_start = MXC_GPIO_IRQ_START + 64, - }, { - .chip.label = "gpio-3", - .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300), - .irq = GPIO_INT_PORTD, - .virtual_irq_start = MXC_GPIO_IRQ_START + 96, - } -}; - -int __init mxc_register_gpios(void) -{ - return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); -} diff --git a/arch/arm/mach-mx1/devices.h b/arch/arm/mach-mx1/devices.h deleted file mode 100644 index 0da5d7cce3a..00000000000 --- a/arch/arm/mach-mx1/devices.h +++ /dev/null @@ -1,7 +0,0 @@ -extern struct platform_device imx_csi_device; -extern struct platform_device imx_i2c_device; -extern struct platform_device imx_uart1_device; -extern struct platform_device imx_uart2_device; -extern struct platform_device imx_rtc_device; -extern struct platform_device imx_wdt_device; -extern struct platform_device imx_usb_device; diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c deleted file mode 100644 index 1c0c835b225..00000000000 --- a/arch/arm/mach-mx2/serial.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/serial.h> -#include <mach/hardware.h> -#include <mach/imx-uart.h> -#include "devices.h" - -static struct resource uart0[] = { - { - .start = MX2x_UART1_BASE_ADDR, - .end = MX2x_UART1_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MX2x_INT_UART1, - .end = MX2x_INT_UART1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device0 = { - .name = "imx-uart", - .id = 0, - .resource = uart0, - .num_resources = ARRAY_SIZE(uart0), -}; - -static struct resource uart1[] = { - { - .start = MX2x_UART2_BASE_ADDR, - .end = MX2x_UART2_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MX2x_INT_UART2, - .end = MX2x_INT_UART2, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device1 = { - .name = "imx-uart", - .id = 1, - .resource = uart1, - .num_resources = ARRAY_SIZE(uart1), -}; - -static struct resource uart2[] = { - { - .start = MX2x_UART3_BASE_ADDR, - .end = MX2x_UART3_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MX2x_INT_UART3, - .end = MX2x_INT_UART3, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device2 = { - .name = "imx-uart", - .id = 2, - .resource = uart2, - .num_resources = ARRAY_SIZE(uart2), -}; - -static struct resource uart3[] = { - { - .start = MX2x_UART4_BASE_ADDR, - .end = MX2x_UART4_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MX2x_INT_UART4, - .end = MX2x_INT_UART4, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device3 = { - .name = "imx-uart", - .id = 3, - .resource = uart3, - .num_resources = ARRAY_SIZE(uart3), -}; - -#ifdef CONFIG_MACH_MX27 -static struct resource uart4[] = { - { - .start = MX27_UART5_BASE_ADDR, - .end = MX27_UART5_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MX27_INT_UART5, - .end = MX27_INT_UART5, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device4 = { - .name = "imx-uart", - .id = 4, - .resource = uart4, - .num_resources = ARRAY_SIZE(uart4), -}; - -static struct resource uart5[] = { - { - .start = MX27_UART6_BASE_ADDR, - .end = MX27_UART6_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MX27_INT_UART6, - .end = MX27_INT_UART6, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device5 = { - .name = "imx-uart", - .id = 5, - .resource = uart5, - .num_resources = ARRAY_SIZE(uart5), -}; -#endif diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig index 54d217314ee..c71a7bc1928 100644 --- a/arch/arm/mach-mx25/Kconfig +++ b/arch/arm/mach-mx25/Kconfig @@ -4,5 +4,28 @@ comment "MX25 platforms:" config MACH_MX25_3DS bool "Support MX25PDK (3DS) Platform" + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND + +config MACH_EUKREA_CPUIMX25 + bool "Support Eukrea CPUIMX25 Platform" + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND + select MXC_ULPI if USB_ULPI + +choice + prompt "Baseboard" + depends on MACH_EUKREA_CPUIMX25 + default MACH_EUKREA_MBIMXSD25_BASEBOARD + +config MACH_EUKREA_MBIMXSD25_BASEBOARD + prompt "Eukrea MBIMXSD development board" + bool + help + This adds board specific devices that can be found on Eukrea's + MBIMXSD evaluation board. + +endchoice endif diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile index 10cebc5ced8..d9e46ce00a4 100644 --- a/arch/arm/mach-mx25/Makefile +++ b/arch/arm/mach-mx25/Makefile @@ -1,3 +1,5 @@ obj-y := mm.o devices.o obj-$(CONFIG_ARCH_MX25) += clock.o -obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25pdk.o +obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o +obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-cpuimx25.o +obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd-baseboard.o diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c index 155014993b1..40c7cc41cee 100644 --- a/arch/arm/mach-mx25/clock.c +++ b/arch/arm/mach-mx25/clock.c @@ -109,6 +109,16 @@ static unsigned long get_rate_uart(struct clk *clk) return get_rate_per(15); } +static unsigned long get_rate_ssi2(struct clk *clk) +{ + return get_rate_per(14); +} + +static unsigned long get_rate_ssi1(struct clk *clk) +{ + return get_rate_per(13); +} + static unsigned long get_rate_i2c(struct clk *clk) { return get_rate_per(6); @@ -129,9 +139,17 @@ static unsigned long get_rate_lcdc(struct clk *clk) return get_rate_per(7); } +static unsigned long get_rate_csi(struct clk *clk) +{ + return get_rate_per(0); +} + static unsigned long get_rate_otg(struct clk *clk) { - return 48000000; /* FIXME */ + unsigned long cctl = readl(CRM_BASE + CCM_CCTL); + unsigned long rate = get_rate_upll(); + + return (cctl & (1 << 23)) ? 0 : rate / ((0x3F & (cctl >> 16)) + 1); } static int clk_cgcr_enable(struct clk *clk) @@ -166,14 +184,40 @@ static void clk_cgcr_disable(struct clk *clk) .secondary = s, \ } +/* + * Note: the following IPG clock gating bits are wrongly marked "Reserved" in + * the i.MX25 Reference Manual Rev 1, table 15-13. The information below is + * taken from the Freescale released BSP. + * + * bit reg offset clock + * + * 0 CGCR1 0 AUDMUX + * 12 CGCR1 12 ESAI + * 16 CGCR1 16 GPIO1 + * 17 CGCR1 17 GPIO2 + * 18 CGCR1 18 GPIO3 + * 23 CGCR1 23 I2C1 + * 24 CGCR1 24 I2C2 + * 25 CGCR1 25 I2C3 + * 27 CGCR1 27 IOMUXC + * 28 CGCR1 28 KPP + * 30 CGCR1 30 OWIRE + * 36 CGCR2 4 RTIC + * 51 CGCR2 19 WDOG + */ + DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_gpt, NULL, NULL); DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL); +DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL); +DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL); DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL); DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk); +DEFINE_CLOCK(csi_ahb_clk, 0, CCM_CGCR0, 18, get_rate_csi, NULL, NULL); +DEFINE_CLOCK(csi_per_clk, 0, CCM_CGCR0, 0, get_rate_csi, NULL, &csi_ahb_clk); DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk); DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk); DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk); @@ -191,6 +235,13 @@ DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL); DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk); DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk); +DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL); +DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk); +DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk); +DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL); +DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk); +DEFINE_CLOCK(can1_clk, 0, CCM_CGCR1, 2, get_rate_ipg, NULL, NULL); +DEFINE_CLOCK(can2_clk, 0, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL); #define _REGISTER_CLOCK(d, n, c) \ { \ @@ -217,7 +268,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk) _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk) _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk) - _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk) + _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk) _REGISTER_CLOCK("mx25-adc", NULL, tsc_clk) _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk) @@ -225,6 +276,13 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("fec.0", NULL, fec_clk) _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk) _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) + _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk) + _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) + _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) + _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk) + _REGISTER_CLOCK(NULL, "audmux", audmux_clk) + _REGISTER_CLOCK("flexcan.0", NULL, can1_clk) + _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) }; int __init mx25_clocks_init(void) @@ -238,9 +296,13 @@ int __init mx25_clocks_init(void) __raw_writel((1 << 19), CRM_BASE + CCM_CGCR0); __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1); __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2); +#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) + clk_enable(&uart1_clk); +#endif - /* Clock source for lcdc is upll */ - __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7), CRM_BASE + 0x64); + /* Clock source for lcdc and csi is upll */ + __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0), + CRM_BASE + 0x64); mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h new file mode 100644 index 00000000000..d86a7c3ca8b --- /dev/null +++ b/arch/arm/mach-mx25/devices-imx25.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/mx25.h> +#include <mach/devices-common.h> + +#define imx25_add_flexcan0(pdata) \ + imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata) +#define imx25_add_flexcan1(pdata) \ + imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata) + +#define imx25_add_imx_i2c0(pdata) \ + imx_add_imx_i2c(0, MX25_I2C1_BASE_ADDR, SZ_16K, MX25_INT_I2C1, pdata) +#define imx25_add_imx_i2c1(pdata) \ + imx_add_imx_i2c(1, MX25_I2C2_BASE_ADDR, SZ_16K, MX25_INT_I2C2, pdata) +#define imx25_add_imx_i2c2(pdata) \ + imx_add_imx_i2c(2, MX25_I2C3_BASE_ADDR, SZ_16K, MX25_INT_I2C3, pdata) + +#define imx25_add_imx_uart0(pdata) \ + imx_add_imx_uart_1irq(0, MX25_UART1_BASE_ADDR, SZ_16K, MX25_INT_UART1, pdata) +#define imx25_add_imx_uart1(pdata) \ + imx_add_imx_uart_1irq(1, MX25_UART2_BASE_ADDR, SZ_16K, MX25_INT_UART2, pdata) +#define imx25_add_imx_uart2(pdata) \ + imx_add_imx_uart_1irq(2, MX25_UART3_BASE_ADDR, SZ_16K, MX25_INT_UART3, pdata) +#define imx25_add_imx_uart3(pdata) \ + imx_add_imx_uart_1irq(3, MX25_UART4_BASE_ADDR, SZ_16K, MX25_INT_UART4, pdata) +#define imx25_add_imx_uart4(pdata) \ + imx_add_imx_uart_1irq(4, MX25_UART5_BASE_ADDR, SZ_16K, MX25_INT_UART5, pdata) + +#define imx25_add_mxc_nand(pdata) \ + imx_add_mxc_nand_v21(MX25_NFC_BASE_ADDR, MX25_INT_NANDFC, pdata) + +#define imx25_add_spi_imx0(pdata) \ + imx_add_spi_imx(0, MX25_CSPI1_BASE_ADDR, SZ_16K, MX25_INT_CSPI1, pdata) +#define imx25_add_spi_imx1(pdata) \ + imx_add_spi_imx(1, MX25_CSPI2_BASE_ADDR, SZ_16K, MX25_INT_CSPI2, pdata) +#define imx25_add_spi_imx2(pdata) \ + imx_add_spi_imx(2, MX25_CSPI3_BASE_ADDR, SZ_16K, MX25_INT_CSPI3, pdata) diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c index 3a405fa400e..3468eb15b23 100644 --- a/arch/arm/mach-mx25/devices.c +++ b/arch/arm/mach-mx25/devices.c @@ -22,103 +22,6 @@ #include <mach/mx25.h> #include <mach/irqs.h> -static struct resource uart0[] = { - { - .start = 0x43f90000, - .end = 0x43f93fff, - .flags = IORESOURCE_MEM, - }, { - .start = 45, - .end = 45, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device0 = { - .name = "imx-uart", - .id = 0, - .resource = uart0, - .num_resources = ARRAY_SIZE(uart0), -}; - -static struct resource uart1[] = { - { - .start = 0x43f94000, - .end = 0x43f97fff, - .flags = IORESOURCE_MEM, - }, { - .start = 32, - .end = 32, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device1 = { - .name = "imx-uart", - .id = 1, - .resource = uart1, - .num_resources = ARRAY_SIZE(uart1), -}; - -static struct resource uart2[] = { - { - .start = 0x5000c000, - .end = 0x5000ffff, - .flags = IORESOURCE_MEM, - }, { - .start = 18, - .end = 18, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device2 = { - .name = "imx-uart", - .id = 2, - .resource = uart2, - .num_resources = ARRAY_SIZE(uart2), -}; - -static struct resource uart3[] = { - { - .start = 0x50008000, - .end = 0x5000bfff, - .flags = IORESOURCE_MEM, - }, { - .start = 5, - .end = 5, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device3 = { - .name = "imx-uart", - .id = 3, - .resource = uart3, - .num_resources = ARRAY_SIZE(uart3), -}; - -static struct resource uart4[] = { - { - .start = 0x5002c000, - .end = 0x5002ffff, - .flags = IORESOURCE_MEM, - }, { - .start = 40, - .end = 40, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device4 = { - .name = "imx-uart", - .id = 4, - .resource = uart4, - .num_resources = ARRAY_SIZE(uart4), -}; - -#define MX25_OTG_BASE_ADDR 0x53FF4000 - static u64 otg_dmamask = DMA_BIT_MASK(32); static struct resource mxc_otg_resources[] = { @@ -181,63 +84,6 @@ struct platform_device mxc_usbh2 = { .num_resources = ARRAY_SIZE(mxc_usbh2_resources), }; -static struct resource mxc_spi_resources0[] = { - { - .start = 0x43fa4000, - .end = 0x43fa7fff, - .flags = IORESOURCE_MEM, - }, { - .start = 14, - .end = 14, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_spi_device0 = { - .name = "spi_imx", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_spi_resources0), - .resource = mxc_spi_resources0, -}; - -static struct resource mxc_spi_resources1[] = { - { - .start = 0x50010000, - .end = 0x50013fff, - .flags = IORESOURCE_MEM, - }, { - .start = 13, - .end = 13, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_spi_device1 = { - .name = "spi_imx", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_spi_resources1), - .resource = mxc_spi_resources1, -}; - -static struct resource mxc_spi_resources2[] = { - { - .start = 0x50004000, - .end = 0x50007fff, - .flags = IORESOURCE_MEM, - }, { - .start = 0, - .end = 0, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_spi_device2 = { - .name = "spi_imx", - .id = 2, - .num_resources = ARRAY_SIZE(mxc_spi_resources2), - .resource = mxc_spi_resources2, -}; - static struct resource mxc_pwm_resources0[] = { { .start = 0x53fe0000, @@ -333,63 +179,6 @@ struct platform_device mxc_pwm_device3 = { .resource = mxc_pwm_resources3, }; -static struct resource mxc_i2c_1_resources[] = { - { - .start = 0x43f80000, - .end = 0x43f83fff, - .flags = IORESOURCE_MEM, - }, { - .start = 3, - .end = 3, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_i2c_device0 = { - .name = "imx-i2c", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_i2c_1_resources), - .resource = mxc_i2c_1_resources, -}; - -static struct resource mxc_i2c_2_resources[] = { - { - .start = 0x43f98000, - .end = 0x43f9bfff, - .flags = IORESOURCE_MEM, - }, { - .start = 4, - .end = 4, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_i2c_device1 = { - .name = "imx-i2c", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_i2c_2_resources), - .resource = mxc_i2c_2_resources, -}; - -static struct resource mxc_i2c_3_resources[] = { - { - .start = 0x43f84000, - .end = 0x43f87fff, - .flags = IORESOURCE_MEM, - }, { - .start = 10, - .end = 10, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_i2c_device2 = { - .name = "imx-i2c", - .id = 2, - .num_resources = ARRAY_SIZE(mxc_i2c_3_resources), - .resource = mxc_i2c_3_resources, -}; - static struct mxc_gpio_port imx_gpio_ports[] = { { .chip.label = "gpio-0", @@ -414,7 +203,7 @@ static struct mxc_gpio_port imx_gpio_ports[] = { } }; -int __init mxc_register_gpios(void) +int __init imx25_register_gpios(void) { return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); } @@ -439,26 +228,6 @@ struct platform_device mx25_fec_device = { .resource = mx25_fec_resources, }; -static struct resource mxc_nand_resources[] = { - { - .start = MX25_NFC_BASE_ADDR, - .end = MX25_NFC_BASE_ADDR + 0x1fff, - .flags = IORESOURCE_MEM, - }, - { - .start = MX25_INT_NANDFC, - .end = MX25_INT_NANDFC, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_nand_device = { - .name = "mxc_nand", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_nand_resources), - .resource = mxc_nand_resources, -}; - static struct resource mx25_rtc_resources[] = { { .start = MX25_DRYICE_BASE_ADDR, @@ -515,3 +284,83 @@ struct platform_device mxc_wdt = { .num_resources = ARRAY_SIZE(mxc_wdt_resources), .resource = mxc_wdt_resources, }; + +static struct resource mx25_kpp_resources[] = { + { + .start = MX25_KPP_BASE_ADDR, + .end = MX25_KPP_BASE_ADDR + 0xf, + .flags = IORESOURCE_MEM, + }, + { + .start = MX25_INT_KPP, + .end = MX25_INT_KPP, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mx25_kpp_device = { + .name = "imx-keypad", + .id = -1, + .num_resources = ARRAY_SIZE(mx25_kpp_resources), + .resource = mx25_kpp_resources, +}; + +static struct resource imx_ssi_resources0[] = { + { + .start = MX25_SSI1_BASE_ADDR, + .end = MX25_SSI1_BASE_ADDR + 0x3fff, + .flags = IORESOURCE_MEM, + }, { + .start = MX25_INT_SSI1, + .end = MX25_INT_SSI1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource imx_ssi_resources1[] = { + { + .start = MX25_SSI2_BASE_ADDR, + .end = MX25_SSI2_BASE_ADDR + 0x3fff, + .flags = IORESOURCE_MEM + }, { + .start = MX25_INT_SSI2, + .end = MX25_INT_SSI2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_ssi_device0 = { + .name = "imx-ssi", + .id = 0, + .num_resources = ARRAY_SIZE(imx_ssi_resources0), + .resource = imx_ssi_resources0, +}; + +struct platform_device imx_ssi_device1 = { + .name = "imx-ssi", + .id = 1, + .num_resources = ARRAY_SIZE(imx_ssi_resources1), + .resource = imx_ssi_resources1, +}; + +static struct resource mx25_csi_resources[] = { + { + .start = MX25_CSI_BASE_ADDR, + .end = MX25_CSI_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + { + .start = MX25_INT_CSI, + .flags = IORESOURCE_IRQ + }, +}; + +struct platform_device mx25_csi_device = { + .name = "mx2-camera", + .id = 0, + .num_resources = ARRAY_SIZE(mx25_csi_resources), + .resource = mx25_csi_resources, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h index cee12c0a0be..4aceb68e35a 100644 --- a/arch/arm/mach-mx25/devices.h +++ b/arch/arm/mach-mx25/devices.h @@ -1,24 +1,16 @@ -extern struct platform_device mxc_uart_device0; -extern struct platform_device mxc_uart_device1; -extern struct platform_device mxc_uart_device2; -extern struct platform_device mxc_uart_device3; -extern struct platform_device mxc_uart_device4; extern struct platform_device mxc_otg; extern struct platform_device otg_udc_device; extern struct platform_device mxc_usbh2; -extern struct platform_device mxc_spi_device0; -extern struct platform_device mxc_spi_device1; -extern struct platform_device mxc_spi_device2; extern struct platform_device mxc_pwm_device0; extern struct platform_device mxc_pwm_device1; extern struct platform_device mxc_pwm_device2; extern struct platform_device mxc_pwm_device3; extern struct platform_device mxc_keypad_device; -extern struct platform_device mxc_i2c_device0; -extern struct platform_device mxc_i2c_device1; -extern struct platform_device mxc_i2c_device2; extern struct platform_device mx25_fec_device; -extern struct platform_device mxc_nand_device; extern struct platform_device mx25_rtc_device; extern struct platform_device mx25_fb_device; extern struct platform_device mxc_wdt; +extern struct platform_device mx25_kpp_device; +extern struct platform_device imx_ssi_device0; +extern struct platform_device imx_ssi_device1; +extern struct platform_device mx25_csi_device; diff --git a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c new file mode 100644 index 00000000000..91931dcb068 --- /dev/null +++ b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c @@ -0,0 +1,260 @@ +/* + * Copyright (C) 2010 Eric Benard - eric@eukrea.com + * + * Based on pcm970-baseboard.c which is : + * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <linux/gpio.h> +#include <linux/leds.h> +#include <linux/platform_device.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <video/platform_lcd.h> + +#include <mach/hardware.h> +#include <mach/iomux-mx25.h> +#include <mach/common.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <mach/mx25.h> +#include <mach/imx-uart.h> +#include <mach/imxfb.h> +#include <mach/ssi.h> +#include <mach/audmux.h> + +#include "devices-imx25.h" +#include "devices.h" + +static struct pad_desc eukrea_mbimxsd_pads[] = { + /* LCD */ + MX25_PAD_LD0__LD0, + MX25_PAD_LD1__LD1, + MX25_PAD_LD2__LD2, + MX25_PAD_LD3__LD3, + MX25_PAD_LD4__LD4, + MX25_PAD_LD5__LD5, + MX25_PAD_LD6__LD6, + MX25_PAD_LD7__LD7, + MX25_PAD_LD8__LD8, + MX25_PAD_LD9__LD9, + MX25_PAD_LD10__LD10, + MX25_PAD_LD11__LD11, + MX25_PAD_LD12__LD12, + MX25_PAD_LD13__LD13, + MX25_PAD_LD14__LD14, + MX25_PAD_LD15__LD15, + MX25_PAD_GPIO_E__LD16, + MX25_PAD_GPIO_F__LD17, + MX25_PAD_HSYNC__HSYNC, + MX25_PAD_VSYNC__VSYNC, + MX25_PAD_LSCLK__LSCLK, + MX25_PAD_OE_ACD__OE_ACD, + MX25_PAD_CONTRAST__CONTRAST, + /* LCD_PWR */ + MX25_PAD_PWM__GPIO_1_26, + /* LED */ + MX25_PAD_POWER_FAIL__GPIO_3_19, + /* SWITCH */ + MX25_PAD_VSTBY_ACK__GPIO_3_18, + /* UART2 */ + MX25_PAD_UART2_RTS__UART2_RTS, + MX25_PAD_UART2_CTS__UART2_CTS, + MX25_PAD_UART2_TXD__UART2_TXD, + MX25_PAD_UART2_RXD__UART2_RXD, + /* SD1 */ + MX25_PAD_SD1_CMD__SD1_CMD, + MX25_PAD_SD1_CLK__SD1_CLK, + MX25_PAD_SD1_DATA0__SD1_DATA0, + MX25_PAD_SD1_DATA1__SD1_DATA1, + MX25_PAD_SD1_DATA2__SD1_DATA2, + MX25_PAD_SD1_DATA3__SD1_DATA3, + /* SD1 CD */ + MX25_PAD_DE_B__GPIO_2_20, + /* I2S */ + MX25_PAD_KPP_COL3__AUD5_TXFS, + MX25_PAD_KPP_COL2__AUD5_TXC, + MX25_PAD_KPP_COL1__AUD5_RXD, + MX25_PAD_KPP_COL0__AUD5_TXD, +}; + +#define GPIO_LED1 83 +#define GPIO_SWITCH1 82 +#define GPIO_SD1CD 52 +#define GPIO_LCDPWR 26 + +static struct imx_fb_videomode eukrea_mximxsd_modes[] = { + { + .mode = { + .name = "CMO-QVGA", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6500), + .left_margin = 30, + .right_margin = 38, + .upper_margin = 20, + .lower_margin = 3, + .hsync_len = 15, + .vsync_len = 4, + }, + .bpp = 16, + .pcr = 0xCAD08B80, + }, +}; + +static struct imx_fb_platform_data eukrea_mximxsd_fb_pdata = { + .mode = eukrea_mximxsd_modes, + .num_modes = ARRAY_SIZE(eukrea_mximxsd_modes), + .pwmr = 0x00A903FF, + .lscr1 = 0x00120300, + .dmacr = 0x00040060, +}; + +static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd, + unsigned int power) +{ + if (power) + gpio_direction_output(GPIO_LCDPWR, 1); + else + gpio_direction_output(GPIO_LCDPWR, 0); +} + +static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = { + .set_power = eukrea_mbimxsd_lcd_power_set, +}; + +static struct platform_device eukrea_mbimxsd_lcd_powerdev = { + .name = "platform-lcd", + .dev.platform_data = &eukrea_mbimxsd_lcd_power_data, +}; + +static struct gpio_led eukrea_mbimxsd_leds[] = { + { + .name = "led1", + .default_trigger = "heartbeat", + .active_low = 1, + .gpio = GPIO_LED1, + }, +}; + +static struct gpio_led_platform_data eukrea_mbimxsd_led_info = { + .leds = eukrea_mbimxsd_leds, + .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds), +}; + +static struct platform_device eukrea_mbimxsd_leds_gpio = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &eukrea_mbimxsd_led_info, + }, +}; + +static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = { + { + .gpio = GPIO_SWITCH1, + .code = BTN_0, + .desc = "BP1", + .active_low = 1, + .wakeup = 1, + }, +}; + +static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = { + .buttons = eukrea_mbimxsd_gpio_buttons, + .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons), +}; + +static struct platform_device eukrea_mbimxsd_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &eukrea_mbimxsd_button_data, + } +}; + +static struct platform_device *platform_devices[] __initdata = { + &eukrea_mbimxsd_leds_gpio, + &eukrea_mbimxsd_button_device, + &eukrea_mbimxsd_lcd_powerdev, +}; + +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = { + { + I2C_BOARD_INFO("tlv320aic23", 0x1a), + }, +}; + +struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = { + .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, +}; + +/* + * system init for baseboard usage. Will be called by cpuimx25 init. + * + * Add platform devices present on this baseboard and init + * them from CPU side as far as required to use them later on + */ +void __init eukrea_mbimxsd_baseboard_init(void) +{ + if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads, + ARRAY_SIZE(eukrea_mbimxsd_pads))) + printk(KERN_ERR "error setting mbimxsd pads !\n"); + +#if defined(CONFIG_SND_SOC_EUKREA_TLV320) + /* SSI unit master I2S codec connected to SSI_AUD5*/ + mxc_audmux_v2_configure_port(0, + MXC_AUDMUX_V2_PTCR_SYN | + MXC_AUDMUX_V2_PTCR_TFSDIR | + MXC_AUDMUX_V2_PTCR_TFSEL(4) | + MXC_AUDMUX_V2_PTCR_TCLKDIR | + MXC_AUDMUX_V2_PTCR_TCSEL(4), + MXC_AUDMUX_V2_PDCR_RXDSEL(4) + ); + mxc_audmux_v2_configure_port(4, + MXC_AUDMUX_V2_PTCR_SYN, + MXC_AUDMUX_V2_PDCR_RXDSEL(0) + ); +#endif + + imx25_add_imx_uart1(&uart_pdata); + mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata); + mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata); + + gpio_request(GPIO_LED1, "LED1"); + gpio_direction_output(GPIO_LED1, 1); + gpio_free(GPIO_LED1); + + gpio_request(GPIO_SWITCH1, "SWITCH1"); + gpio_direction_input(GPIO_SWITCH1); + gpio_free(GPIO_SWITCH1); + + gpio_request(GPIO_LCDPWR, "LCDPWR"); + gpio_direction_output(GPIO_LCDPWR, 1); + gpio_free(GPIO_SWITCH1); + + i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices, + ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); + + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); +} diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-mx25/mach-cpuimx25.c new file mode 100644 index 00000000000..56b2e26d23b --- /dev/null +++ b/arch/arm/mach-mx25/mach-cpuimx25.c @@ -0,0 +1,173 @@ +/* + * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de> + * Copyright 2010 Eric Bénard - Eukréa Electromatique, <eric@eukrea.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA. + */ + +#include <linux/types.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/irq.h> +#include <linux/gpio.h> +#include <linux/fec.h> +#include <linux/platform_device.h> +#include <linux/usb/otg.h> +#include <linux/usb/ulpi.h> +#include <linux/fsl_devices.h> + +#include <mach/eukrea-baseboards.h> +#include <mach/hardware.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/memory.h> +#include <asm/mach/map.h> +#include <mach/common.h> +#include <mach/mx25.h> +#include <mach/mxc_nand.h> +#include <mach/imxfb.h> +#include <mach/mxc_ehci.h> +#include <mach/ulpi.h> +#include <mach/iomux-mx25.h> + +#include "devices-imx25.h" +#include "devices.h" + +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static struct pad_desc eukrea_cpuimx25_pads[] = { + /* FEC - RMII */ + MX25_PAD_FEC_MDC__FEC_MDC, + MX25_PAD_FEC_MDIO__FEC_MDIO, + MX25_PAD_FEC_TDATA0__FEC_TDATA0, + MX25_PAD_FEC_TDATA1__FEC_TDATA1, + MX25_PAD_FEC_TX_EN__FEC_TX_EN, + MX25_PAD_FEC_RDATA0__FEC_RDATA0, + MX25_PAD_FEC_RDATA1__FEC_RDATA1, + MX25_PAD_FEC_RX_DV__FEC_RX_DV, + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, + /* I2C1 */ + MX25_PAD_I2C1_CLK__I2C1_CLK, + MX25_PAD_I2C1_DAT__I2C1_DAT, +}; + +static struct fec_platform_data mx25_fec_pdata = { + .phy = PHY_INTERFACE_MODE_RMII, +}; + +static const struct mxc_nand_platform_data +eukrea_cpuimx25_nand_board_info __initconst = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + +static const struct imxi2c_platform_data +eukrea_cpuimx25_i2c0_data __initconst = { + .bitrate = 100000, +}; + +static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = { + { + I2C_BOARD_INFO("pcf8563", 0x51), + }, +}; + +static struct mxc_usbh_platform_data otg_pdata = { + .portsc = MXC_EHCI_MODE_UTMI, + .flags = MXC_EHCI_INTERFACE_DIFF_UNI, +}; + +static struct mxc_usbh_platform_data usbh2_pdata = { + .portsc = MXC_EHCI_MODE_SERIAL, + .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | + MXC_EHCI_IPPUE_DOWN, +}; + +static struct fsl_usb2_platform_data otg_device_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_UTMI, +}; + +static int otg_mode_host; + +static int __init eukrea_cpuimx25_otg_mode(char *options) +{ + if (!strcmp(options, "host")) + otg_mode_host = 1; + else if (!strcmp(options, "device")) + otg_mode_host = 0; + else + pr_info("otg_mode neither \"host\" nor \"device\". " + "Defaulting to device\n"); + return 0; +} +__setup("otg_mode=", eukrea_cpuimx25_otg_mode); + +static void __init eukrea_cpuimx25_init(void) +{ + if (mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads, + ARRAY_SIZE(eukrea_cpuimx25_pads))) + printk(KERN_ERR "error setting cpuimx25 pads !\n"); + + imx25_add_imx_uart0(&uart_pdata); + imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info); + mxc_register_device(&mx25_rtc_device, NULL); + mxc_register_device(&mx25_fec_device, &mx25_fec_pdata); + + i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices, + ARRAY_SIZE(eukrea_cpuimx25_i2c_devices)); + imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data); + +#if defined(CONFIG_USB_ULPI) + if (otg_mode_host) { + otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_otg, &otg_pdata); + } + mxc_register_device(&mxc_usbh2, &usbh2_pdata); +#endif + if (!otg_mode_host) + mxc_register_device(&otg_udc_device, &otg_device_pdata); + +#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD + eukrea_mbimxsd_baseboard_init(); +#endif +} + +static void __init eukrea_cpuimx25_timer_init(void) +{ + mx25_clocks_init(); +} + +static struct sys_timer eukrea_cpuimx25_timer = { + .init = eukrea_cpuimx25_timer_init, +}; + +MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25") + /* Maintainer: Eukrea Electromatique */ + .phys_io = MX25_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = MX25_PHYS_OFFSET + 0x100, + .map_io = mx25_map_io, + .init_irq = mx25_init_irq, + .init_machine = eukrea_cpuimx25_init, + .timer = &eukrea_cpuimx25_timer, +MACHINE_END diff --git a/arch/arm/mach-mx25/mach-mx25pdk.c b/arch/arm/mach-mx25/mach-mx25_3ds.c index 83d74109e7d..62bc21f11a7 100644 --- a/arch/arm/mach-mx25/mach-mx25pdk.c +++ b/arch/arm/mach-mx25/mach-mx25_3ds.c @@ -16,6 +16,12 @@ * Boston, MA 02110-1301, USA. */ +/* + * This machine is known as: + * - i.MX25 3-Stack Development System + * - i.MX25 Platform Development Kit (i.MX25 PDK) + */ + #include <linux/types.h> #include <linux/init.h> #include <linux/delay.h> @@ -24,6 +30,7 @@ #include <linux/gpio.h> #include <linux/fec.h> #include <linux/platform_device.h> +#include <linux/input/matrix_keypad.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -32,14 +39,14 @@ #include <asm/memory.h> #include <asm/mach/map.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/mx25.h> -#include <mach/mxc_nand.h> #include <mach/imxfb.h> -#include "devices.h" #include <mach/iomux-mx25.h> -static struct imxuart_platform_data uart_pdata = { +#include "devices-imx25.h" +#include "devices.h" + +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -80,6 +87,16 @@ static struct pad_desc mx25pdk_pads[] = { MX25_PAD_LSCLK__LSCLK, MX25_PAD_OE_ACD__OE_ACD, MX25_PAD_CONTRAST__CONTRAST, + + /* Keypad */ + MX25_PAD_KPP_ROW0__KPP_ROW0, + MX25_PAD_KPP_ROW1__KPP_ROW1, + MX25_PAD_KPP_ROW2__KPP_ROW2, + MX25_PAD_KPP_ROW3__KPP_ROW3, + MX25_PAD_KPP_COL0__KPP_COL0, + MX25_PAD_KPP_COL1__KPP_COL1, + MX25_PAD_KPP_COL2__KPP_COL2, + MX25_PAD_KPP_COL3__KPP_COL3, }; static struct fec_platform_data mx25_fec_pdata = { @@ -103,7 +120,8 @@ static void __init mx25pdk_fec_reset(void) gpio_set_value(FEC_RESET_B_GPIO, 1); } -static struct mxc_nand_platform_data mx25pdk_nand_board_info = { +static const struct mxc_nand_platform_data +mx25pdk_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, .flash_bbt = 1, @@ -137,19 +155,45 @@ static struct imx_fb_platform_data mx25pdk_fb_pdata = { .dmacr = 0x00020010, }; +static const uint32_t mx25pdk_keymap[] = { + KEY(0, 0, KEY_UP), + KEY(0, 1, KEY_DOWN), + KEY(0, 2, KEY_VOLUMEDOWN), + KEY(0, 3, KEY_HOME), + KEY(1, 0, KEY_RIGHT), + KEY(1, 1, KEY_LEFT), + KEY(1, 2, KEY_ENTER), + KEY(1, 3, KEY_VOLUMEUP), + KEY(2, 0, KEY_F6), + KEY(2, 1, KEY_F8), + KEY(2, 2, KEY_F9), + KEY(2, 3, KEY_F10), + KEY(3, 0, KEY_F1), + KEY(3, 1, KEY_F2), + KEY(3, 2, KEY_F3), + KEY(3, 3, KEY_POWER), +}; + +static struct matrix_keymap_data mx25pdk_keymap_data = { + .keymap = mx25pdk_keymap, + .keymap_size = ARRAY_SIZE(mx25pdk_keymap), +}; + static void __init mx25pdk_init(void) { mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, ARRAY_SIZE(mx25pdk_pads)); - mxc_register_device(&mxc_uart_device0, &uart_pdata); + imx25_add_imx_uart0(&uart_pdata); mxc_register_device(&mxc_usbh2, NULL); - mxc_register_device(&mxc_nand_device, &mx25pdk_nand_board_info); + imx25_add_mxc_nand(&mx25pdk_nand_board_info); mxc_register_device(&mx25_rtc_device, NULL); mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata); + mxc_register_device(&mxc_wdt, NULL); mx25pdk_fec_reset(); mxc_register_device(&mx25_fec_device, &mx25_fec_pdata); + mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data); } static void __init mx25pdk_timer_init(void) diff --git a/arch/arm/mach-mx25/mm.c b/arch/arm/mach-mx25/mm.c index a7e587ff3e9..bb677111fb0 100644 --- a/arch/arm/mach-mx25/mm.c +++ b/arch/arm/mach-mx25/mm.c @@ -14,10 +14,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/mm.h> @@ -69,8 +65,11 @@ void __init mx25_map_io(void) iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); } +int imx25_register_gpios(void); + void __init mx25_init_irq(void) { mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT); + imx25_register_gpios(); } diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 344753fdf25..85beece802a 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -15,6 +15,8 @@ comment "MX3 platforms:" config MACH_MX31ADS bool "Support MX31ADS platforms" select ARCH_MX31 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART default y help Include support for MX31ADS platform. This includes specific @@ -34,6 +36,9 @@ config MACH_MX31ADS_WM1133_EV1 config MACH_PCM037 bool "Support Phytec pcm037 (i.MX31) platforms" select ARCH_MX31 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND select MXC_ULPI if USB_ULPI help Include support for Phytec pcm037 platform. This includes @@ -42,6 +47,7 @@ config MACH_PCM037 config MACH_PCM037_EET bool "Support pcm037 EET board extensions" depends on MACH_PCM037 + select IMX_HAVE_PLATFORM_SPI_IMX help Add support for PCM037 EET baseboard extensions. If you are using the OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel @@ -51,6 +57,9 @@ config MACH_MX31LITE bool "Support MX31 LITEKIT (LogicPD)" select ARCH_MX31 select MXC_ULPI if USB_ULPI + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_SPI_IMX help Include support for MX31 LITEKIT platform. This includes specific configurations for the board and its peripherals. @@ -58,6 +67,10 @@ config MACH_MX31LITE config MACH_MX31_3DS bool "Support MX31PDK (3DS)" select ARCH_MX31 + select MXC_DEBUG_BOARD + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_SPI_IMX help Include support for MX31PDK (3DS) platform. This includes specific configurations for the board and its peripherals. @@ -74,6 +87,9 @@ config MACH_MX31_3DS_MXC_NAND_USE_BBT config MACH_MX31MOBOARD bool "Support mx31moboard platforms (EPFL Mobots group)" select ARCH_MX31 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI help Include support for mx31moboard platform. This includes specific @@ -82,6 +98,8 @@ config MACH_MX31MOBOARD config MACH_MX31LILLY bool "Support MX31 LILLY-1131 platforms (INCO startec)" select ARCH_MX31 + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI help Include support for mx31 based LILLY1131 modules. This includes @@ -90,6 +108,7 @@ config MACH_MX31LILLY config MACH_QONG bool "Support Dave/DENX QongEVB-LITE platform" select ARCH_MX31 + select IMX_HAVE_PLATFORM_IMX_UART help Include support for Dave/DENX QongEVB-LITE platform. This includes specific configurations for the board and its peripherals. @@ -97,6 +116,10 @@ config MACH_QONG config MACH_PCM043 bool "Support Phytec pcm043 (i.MX35) platforms" select ARCH_MX35 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_FLEXCAN select MXC_ULPI if USB_ULPI help Include support for Phytec pcm043 platform. This includes @@ -105,6 +128,9 @@ config MACH_PCM043 config MACH_ARMADILLO5X0 bool "Support Atmark Armadillo-500 Development Base Board" select ARCH_MX31 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND select MXC_ULPI if USB_ULPI help Include support for Atmark Armadillo-500 platform. This includes @@ -113,6 +139,7 @@ config MACH_ARMADILLO5X0 config MACH_MX35_3DS bool "Support MX35PDK platform" select ARCH_MX35 + select IMX_HAVE_PLATFORM_IMX_UART default n help Include support for MX35PDK platform. This includes specific @@ -121,8 +148,34 @@ config MACH_MX35_3DS config MACH_KZM_ARM11_01 bool "Support KZM-ARM11-01(Kyoto Microcomputer)" select ARCH_MX31 + select IMX_HAVE_PLATFORM_IMX_UART help Include support for KZM-ARM11-01. This includes specific configurations for the board and its peripherals. +config MACH_EUKREA_CPUIMX35 + bool "Support Eukrea CPUIMX35 Platform" + select ARCH_MX35 + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_MXC_NAND + select MXC_ULPI if USB_ULPI + help + Include support for Eukrea CPUIMX35 platform. This includes + specific configurations for the board and its peripherals. + +choice + prompt "Baseboard" + depends on MACH_EUKREA_CPUIMX35 + default MACH_EUKREA_MBIMXSD35_BASEBOARD + +config MACH_EUKREA_MBIMXSD35_BASEBOARD + prompt "Eukrea MBIMXSD development board" + bool + help + This adds board specific devices that can be found on Eukrea's + MBIMXSD evaluation board. + +endchoice + endif diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 5d650fda5d5..2bd7beceb99 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile @@ -22,5 +22,7 @@ obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \ obj-$(CONFIG_MACH_QONG) += mach-qong.o obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o -obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35pdk.o +obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o +obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o +obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd-baseboard.o diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index 9f3e943e223..d3af0fdf847 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c @@ -359,7 +359,7 @@ DEFINE_CLOCK(i2c1_clk, 0, CCM_CGR1, 10, get_rate_ipg_per, NULL); DEFINE_CLOCK(i2c2_clk, 1, CCM_CGR1, 12, get_rate_ipg_per, NULL); DEFINE_CLOCK(i2c3_clk, 2, CCM_CGR1, 14, get_rate_ipg_per, NULL); DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL); -DEFINE_CLOCK(ipu_clk, 0, CCM_CGR1, 18, NULL, NULL); +DEFINE_CLOCK(ipu_clk, 0, CCM_CGR1, 18, get_rate_ahb, NULL); DEFINE_CLOCK(kpp_clk, 0, CCM_CGR1, 20, get_rate_ipg, NULL); DEFINE_CLOCK(mlb_clk, 0, CCM_CGR1, 22, get_rate_ahb, NULL); DEFINE_CLOCK(mshc_clk, 0, CCM_CGR1, 24, get_rate_mshc, NULL); @@ -428,8 +428,8 @@ static struct clk nfc_clk = { static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "asrc", asrc_clk) _REGISTER_CLOCK(NULL, "ata", ata_clk) - _REGISTER_CLOCK(NULL, "can", can1_clk) - _REGISTER_CLOCK(NULL, "can", can2_clk) + _REGISTER_CLOCK("flexcan.0", NULL, can1_clk) + _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) _REGISTER_CLOCK(NULL, "ect", ect_clk) diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h new file mode 100644 index 00000000000..3b1a44a2058 --- /dev/null +++ b/arch/arm/mach-mx3/devices-imx31.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/mx31.h> +#include <mach/devices-common.h> + +#define imx31_add_imx_i2c0(pdata) \ + imx_add_imx_i2c(0, MX31_I2C1_BASE_ADDR, SZ_4K, MX31_INT_I2C1, pdata) +#define imx31_add_imx_i2c1(pdata) \ + imx_add_imx_i2c(1, MX31_I2C2_BASE_ADDR, SZ_4K, MX31_INT_I2C2, pdata) +#define imx31_add_imx_i2c2(pdata) \ + imx_add_imx_i2c(2, MX31_I2C3_BASE_ADDR, SZ_4K, MX31_INT_I2C3, pdata) + +#define imx31_add_imx_uart0(pdata) \ + imx_add_imx_uart_1irq(0, MX31_UART1_BASE_ADDR, SZ_16K, MX31_INT_UART1, pdata) +#define imx31_add_imx_uart1(pdata) \ + imx_add_imx_uart_1irq(1, MX31_UART2_BASE_ADDR, SZ_16K, MX31_INT_UART2, pdata) +#define imx31_add_imx_uart2(pdata) \ + imx_add_imx_uart_1irq(2, MX31_UART3_BASE_ADDR, SZ_16K, MX31_INT_UART3, pdata) +#define imx31_add_imx_uart3(pdata) \ + imx_add_imx_uart_1irq(3, MX31_UART4_BASE_ADDR, SZ_16K, MX31_INT_UART4, pdata) +#define imx31_add_imx_uart4(pdata) \ + imx_add_imx_uart_1irq(4, MX31_UART5_BASE_ADDR, SZ_16K, MX31_INT_UART5, pdata) + +#define imx31_add_mxc_nand(pdata) \ + imx_add_mxc_nand_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC, pdata) + +#define imx31_add_spi_imx0(pdata) \ + imx_add_spi_imx(0, MX31_CSPI1_BASE_ADDR, SZ_4K, MX31_INT_CSPI1, pdata) +#define imx31_add_spi_imx1(pdata) \ + imx_add_spi_imx(1, MX31_CSPI2_BASE_ADDR, SZ_4K, MX31_INT_CSPI2, pdata) +#define imx31_add_spi_imx2(pdata) \ + imx_add_spi_imx(2, MX31_CSPI3_BASE_ADDR, SZ_4K, MX31_INT_CSPI3, pdata) diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h new file mode 100644 index 00000000000..f6a431a4c3d --- /dev/null +++ b/arch/arm/mach-mx3/devices-imx35.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/mx35.h> +#include <mach/devices-common.h> + +#define imx35_add_flexcan0(pdata) \ + imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata) +#define imx35_add_flexcan1(pdata) \ + imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata) + +#define imx35_add_imx_i2c0(pdata) \ + imx_add_imx_i2c(0, MX35_I2C1_BASE_ADDR, SZ_4K, MX35_INT_I2C1, pdata) +#define imx35_add_imx_i2c1(pdata) \ + imx_add_imx_i2c(1, MX35_I2C2_BASE_ADDR, SZ_4K, MX35_INT_I2C2, pdata) +#define imx35_add_imx_i2c2(pdata) \ + imx_add_imx_i2c(2, MX35_I2C3_BASE_ADDR, SZ_4K, MX35_INT_I2C3, pdata) + +#define imx35_add_imx_uart0(pdata) \ + imx_add_imx_uart_1irq(0, MX35_UART1_BASE_ADDR, SZ_16K, MX35_INT_UART1, pdata) +#define imx35_add_imx_uart1(pdata) \ + imx_add_imx_uart_1irq(1, MX35_UART2_BASE_ADDR, SZ_16K, MX35_INT_UART2, pdata) +#define imx35_add_imx_uart2(pdata) \ + imx_add_imx_uart_1irq(2, MX35_UART3_BASE_ADDR, SZ_16K, MX35_INT_UART3, pdata) + +#define imx35_add_mxc_nand(pdata) \ + imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata) + +#define imx35_add_spi_imx0(pdata) \ + imx_add_spi_imx(0, MX35_CSPI1_BASE_ADDR, SZ_4K, MX35_INT_CSPI1, pdata) +#define imx35_add_spi_imx1(pdata) \ + imx_add_spi_imx(1, MX35_CSPI2_BASE_ADDR, SZ_4K, MX35_INT_CSPI2, pdata) diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index db7acd6e910..a4fd1a26fc9 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c @@ -25,108 +25,10 @@ #include <mach/hardware.h> #include <mach/irqs.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/mx3_camera.h> #include "devices.h" -static struct resource uart0[] = { - { - .start = UART1_BASE_ADDR, - .end = UART1_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_UART1, - .end = MXC_INT_UART1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device0 = { - .name = "imx-uart", - .id = 0, - .resource = uart0, - .num_resources = ARRAY_SIZE(uart0), -}; - -static struct resource uart1[] = { - { - .start = UART2_BASE_ADDR, - .end = UART2_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_UART2, - .end = MXC_INT_UART2, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device1 = { - .name = "imx-uart", - .id = 1, - .resource = uart1, - .num_resources = ARRAY_SIZE(uart1), -}; - -static struct resource uart2[] = { - { - .start = UART3_BASE_ADDR, - .end = UART3_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_UART3, - .end = MXC_INT_UART3, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device2 = { - .name = "imx-uart", - .id = 2, - .resource = uart2, - .num_resources = ARRAY_SIZE(uart2), -}; - -#ifdef CONFIG_ARCH_MX31 -static struct resource uart3[] = { - { - .start = UART4_BASE_ADDR, - .end = UART4_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_UART4, - .end = MXC_INT_UART4, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device3 = { - .name = "imx-uart", - .id = 3, - .resource = uart3, - .num_resources = ARRAY_SIZE(uart3), -}; - -static struct resource uart4[] = { - { - .start = UART5_BASE_ADDR, - .end = UART5_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_UART5, - .end = MXC_INT_UART5, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device4 = { - .name = "imx-uart", - .id = 4, - .resource = uart4, - .num_resources = ARRAY_SIZE(uart4), -}; -#endif /* CONFIG_ARCH_MX31 */ - /* GPIO port description */ static struct mxc_gpio_port imx_gpio_ports[] = { { @@ -147,7 +49,7 @@ static struct mxc_gpio_port imx_gpio_ports[] = { } }; -int __init mxc_register_gpios(void) +int __init imx3x_register_gpios(void) { return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); } @@ -167,82 +69,6 @@ struct platform_device mxc_w1_master_device = { .resource = mxc_w1_master_resources, }; -static struct resource mxc_nand_resources[] = { - { - .start = 0, /* runtime dependent */ - .end = 0, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_NANDFC, - .end = MXC_INT_NANDFC, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_nand_device = { - .name = "mxc_nand", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_nand_resources), - .resource = mxc_nand_resources, -}; - -static struct resource mxc_i2c0_resources[] = { - { - .start = I2C_BASE_ADDR, - .end = I2C_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_I2C, - .end = MXC_INT_I2C, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_i2c_device0 = { - .name = "imx-i2c", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_i2c0_resources), - .resource = mxc_i2c0_resources, -}; - -static struct resource mxc_i2c1_resources[] = { - { - .start = I2C2_BASE_ADDR, - .end = I2C2_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_I2C2, - .end = MXC_INT_I2C2, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_i2c_device1 = { - .name = "imx-i2c", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_i2c1_resources), - .resource = mxc_i2c1_resources, -}; - -static struct resource mxc_i2c2_resources[] = { - { - .start = I2C3_BASE_ADDR, - .end = I2C3_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_I2C3, - .end = MXC_INT_I2C3, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_i2c_device2 = { - .name = "imx-i2c", - .id = 2, - .num_resources = ARRAY_SIZE(mxc_i2c2_resources), - .resource = mxc_i2c2_resources, -}; - #ifdef CONFIG_ARCH_MX31 static struct resource mxcsdhc0_resources[] = { { @@ -455,68 +281,7 @@ struct platform_device mxc_usbh2 = { .num_resources = ARRAY_SIZE(mxc_usbh2_resources), }; -/* - * SPI master controller - * 3 channels - */ -static struct resource mxc_spi_0_resources[] = { - { - .start = CSPI1_BASE_ADDR, - .end = CSPI1_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_CSPI1, - .end = MXC_INT_CSPI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource mxc_spi_1_resources[] = { - { - .start = CSPI2_BASE_ADDR, - .end = CSPI2_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_CSPI2, - .end = MXC_INT_CSPI2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource mxc_spi_2_resources[] = { - { - .start = CSPI3_BASE_ADDR, - .end = CSPI3_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_CSPI3, - .end = MXC_INT_CSPI3, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_spi_device0 = { - .name = "spi_imx", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_spi_0_resources), - .resource = mxc_spi_0_resources, -}; - -struct platform_device mxc_spi_device1 = { - .name = "spi_imx", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_spi_1_resources), - .resource = mxc_spi_1_resources, -}; - -struct platform_device mxc_spi_device2 = { - .name = "spi_imx", - .id = 2, - .num_resources = ARRAY_SIZE(mxc_spi_2_resources), - .resource = mxc_spi_2_resources, -}; - -#ifdef CONFIG_ARCH_MX35 +#if defined(CONFIG_ARCH_MX35) static struct resource mxc_fec_resources[] = { { .start = MXC_FEC_BASE_ADDR, @@ -628,16 +393,15 @@ struct platform_device imx_kpp_device = { static int __init mx3_devices_init(void) { +#if defined(CONFIG_ARCH_MX31) if (cpu_is_mx31()) { - mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR; - mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff; imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR; imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff; mxc_register_device(&mxc_rnga_device, NULL); } +#endif +#if defined(CONFIG_ARCH_MX35) if (cpu_is_mx35()) { - mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR; - mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0x1fff; otg_resources[0].start = MX35_OTG_BASE_ADDR; otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff; otg_resources[1].start = MXC_INT_USBOTG; @@ -653,6 +417,7 @@ static int __init mx3_devices_init(void) imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR; imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff; } +#endif return 0; } diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h index 2c3c8646a29..e5535234839 100644 --- a/arch/arm/mach-mx3/devices.h +++ b/arch/arm/mach-mx3/devices.h @@ -1,14 +1,4 @@ - -extern struct platform_device mxc_uart_device0; -extern struct platform_device mxc_uart_device1; -extern struct platform_device mxc_uart_device2; -extern struct platform_device mxc_uart_device3; -extern struct platform_device mxc_uart_device4; extern struct platform_device mxc_w1_master_device; -extern struct platform_device mxc_nand_device; -extern struct platform_device mxc_i2c_device0; -extern struct platform_device mxc_i2c_device1; -extern struct platform_device mxc_i2c_device2; extern struct platform_device mx3_ipu; extern struct platform_device mx3_fb; extern struct platform_device mx3_camera; @@ -20,9 +10,6 @@ extern struct platform_device mxc_otg_host; extern struct platform_device mxc_usbh1; extern struct platform_device mxc_usbh2; extern struct platform_device mxc_rnga_device; -extern struct platform_device mxc_spi_device0; -extern struct platform_device mxc_spi_device1; -extern struct platform_device mxc_spi_device2; extern struct platform_device imx_ssi_device0; extern struct platform_device imx_ssi_device1; extern struct platform_device imx_ssi_device1; diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c new file mode 100644 index 00000000000..1dc5004df86 --- /dev/null +++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c @@ -0,0 +1,263 @@ +/* + * Copyright (C) 2010 Eric Benard - eric@eukrea.com + * + * Based on pcm970-baseboard.c which is : + * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <linux/types.h> +#include <linux/init.h> + +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/leds.h> +#include <linux/platform_device.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <video/platform_lcd.h> +#include <linux/i2c.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/mach/map.h> + +#include <mach/hardware.h> +#include <mach/common.h> +#include <mach/imx-uart.h> +#include <mach/iomux-mx35.h> +#include <mach/ipu.h> +#include <mach/mx3fb.h> +#include <mach/audmux.h> +#include <mach/ssi.h> + +#include "devices-imx35.h" +#include "devices.h" + +static const struct fb_videomode fb_modedb[] = { + { + .name = "CMO_QVGA", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6500), + .left_margin = 68, + .right_margin = 20, + .upper_margin = 15, + .lower_margin = 4, + .hsync_len = 30, + .vsync_len = 3, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }, +}; + +static struct ipu_platform_data mx3_ipu_data = { + .irq_base = MXC_IPU_IRQ_START, +}; + +static struct mx3fb_platform_data mx3fb_pdata = { + .dma_dev = &mx3_ipu.dev, + .name = "CMO_QVGA", + .mode = fb_modedb, + .num_modes = ARRAY_SIZE(fb_modedb), +}; + +static struct pad_desc eukrea_mbimxsd_pads[] = { + /* LCD */ + MX35_PAD_LD0__IPU_DISPB_DAT_0, + MX35_PAD_LD1__IPU_DISPB_DAT_1, + MX35_PAD_LD2__IPU_DISPB_DAT_2, + MX35_PAD_LD3__IPU_DISPB_DAT_3, + MX35_PAD_LD4__IPU_DISPB_DAT_4, + MX35_PAD_LD5__IPU_DISPB_DAT_5, + MX35_PAD_LD6__IPU_DISPB_DAT_6, + MX35_PAD_LD7__IPU_DISPB_DAT_7, + MX35_PAD_LD8__IPU_DISPB_DAT_8, + MX35_PAD_LD9__IPU_DISPB_DAT_9, + MX35_PAD_LD10__IPU_DISPB_DAT_10, + MX35_PAD_LD11__IPU_DISPB_DAT_11, + MX35_PAD_LD12__IPU_DISPB_DAT_12, + MX35_PAD_LD13__IPU_DISPB_DAT_13, + MX35_PAD_LD14__IPU_DISPB_DAT_14, + MX35_PAD_LD15__IPU_DISPB_DAT_15, + MX35_PAD_LD16__IPU_DISPB_DAT_16, + MX35_PAD_LD17__IPU_DISPB_DAT_17, + MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, + MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, + MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, + MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, + /* Backlight */ + MX35_PAD_CONTRAST__IPU_DISPB_CONTR, + /* LCD_PWR */ + MX35_PAD_D3_CLS__GPIO1_4, + /* LED */ + MX35_PAD_LD23__GPIO3_29, + /* SWITCH */ + MX35_PAD_LD19__GPIO3_25, + /* UART2 */ + MX35_PAD_CTS2__UART2_CTS, + MX35_PAD_RTS2__UART2_RTS, + MX35_PAD_TXD2__UART2_TXD_MUX, + MX35_PAD_RXD2__UART2_RXD_MUX, + /* I2S */ + MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS, + MX35_PAD_STXD4__AUDMUX_AUD4_TXD, + MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, + MX35_PAD_SCK4__AUDMUX_AUD4_TXC, +}; + +#define GPIO_LED1 (2 * 32 + 29) +#define GPIO_SWITCH1 (2 * 32 + 25) +#define GPIO_LCDPWR (4) + +static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd, + unsigned int power) +{ + if (power) + gpio_direction_output(GPIO_LCDPWR, 1); + else + gpio_direction_output(GPIO_LCDPWR, 0); +} + +static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = { + .set_power = eukrea_mbimxsd_lcd_power_set, +}; + +static struct platform_device eukrea_mbimxsd_lcd_powerdev = { + .name = "platform-lcd", + .dev.platform_data = &eukrea_mbimxsd_lcd_power_data, +}; + +static struct gpio_led eukrea_mbimxsd_leds[] = { + { + .name = "led1", + .default_trigger = "heartbeat", + .active_low = 1, + .gpio = GPIO_LED1, + }, +}; + +static struct gpio_led_platform_data eukrea_mbimxsd_led_info = { + .leds = eukrea_mbimxsd_leds, + .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds), +}; + +static struct platform_device eukrea_mbimxsd_leds_gpio = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &eukrea_mbimxsd_led_info, + }, +}; + +static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = { + { + .gpio = GPIO_SWITCH1, + .code = BTN_0, + .desc = "BP1", + .active_low = 1, + .wakeup = 1, + }, +}; + +static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = { + .buttons = eukrea_mbimxsd_gpio_buttons, + .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons), +}; + +static struct platform_device eukrea_mbimxsd_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &eukrea_mbimxsd_button_data, + } +}; + +static struct platform_device *platform_devices[] __initdata = { + &eukrea_mbimxsd_leds_gpio, + &eukrea_mbimxsd_button_device, + &eukrea_mbimxsd_lcd_powerdev, +}; + +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = { + { + I2C_BOARD_INFO("tlv320aic23", 0x1a), + }, +}; + +struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = { + .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, +}; + +/* + * system init for baseboard usage. Will be called by cpuimx35 init. + * + * Add platform devices present on this baseboard and init + * them from CPU side as far as required to use them later on + */ +void __init eukrea_mbimxsd_baseboard_init(void) +{ + if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads, + ARRAY_SIZE(eukrea_mbimxsd_pads))) + printk(KERN_ERR "error setting mbimxsd pads !\n"); + +#if defined(CONFIG_SND_SOC_EUKREA_TLV320) + /* SSI unit master I2S codec connected to SSI_AUD4 */ + mxc_audmux_v2_configure_port(0, + MXC_AUDMUX_V2_PTCR_SYN | + MXC_AUDMUX_V2_PTCR_TFSDIR | + MXC_AUDMUX_V2_PTCR_TFSEL(3) | + MXC_AUDMUX_V2_PTCR_TCLKDIR | + MXC_AUDMUX_V2_PTCR_TCSEL(3), + MXC_AUDMUX_V2_PDCR_RXDSEL(3) + ); + mxc_audmux_v2_configure_port(3, + MXC_AUDMUX_V2_PTCR_SYN, + MXC_AUDMUX_V2_PDCR_RXDSEL(0) + ); +#endif + + imx35_add_imx_uart1(&uart_pdata); + mxc_register_device(&mx3_ipu, &mx3_ipu_data); + mxc_register_device(&mx3_fb, &mx3fb_pdata); + + mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata); + + gpio_request(GPIO_LED1, "LED1"); + gpio_direction_output(GPIO_LED1, 1); + gpio_free(GPIO_LED1); + + gpio_request(GPIO_SWITCH1, "SWITCH1"); + gpio_direction_input(GPIO_SWITCH1); + gpio_free(GPIO_SWITCH1); + + gpio_request(GPIO_LCDPWR, "LCDPWR"); + gpio_direction_output(GPIO_LCDPWR, 1); + gpio_free(GPIO_SWITCH1); + + i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices, + ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); + + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); +} diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c index 5f72ec91af2..96aadcadb4f 100644 --- a/arch/arm/mach-mx3/mach-armadillo5x0.c +++ b/arch/arm/mach-mx3/mach-armadillo5x0.c @@ -48,16 +48,14 @@ #include <asm/mach/map.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> -#include <mach/board-armadillo5x0.h> #include <mach/mmc.h> #include <mach/ipu.h> #include <mach/mx3fb.h> -#include <mach/mxc_nand.h> #include <mach/mxc_ehci.h> #include <mach/ulpi.h> +#include "devices-imx31.h" #include "devices.h" #include "crm_regs.h" @@ -301,7 +299,8 @@ static struct platform_device armadillo5x0_button_device = { /* * NAND Flash */ -static struct mxc_nand_platform_data armadillo5x0_nand_flash_pdata = { +static const struct mxc_nand_platform_data +armadillo5x0_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, }; @@ -493,13 +492,12 @@ static struct platform_device armadillo5x0_smc911x_device = { }; /* UART device data */ -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; static struct platform_device *devices[] __initdata = { &armadillo5x0_smc911x_device, - &mxc_i2c_device1, &armadillo5x0_button_device, }; @@ -512,10 +510,11 @@ static void __init armadillo5x0_init(void) ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0"); platform_add_devices(devices, ARRAY_SIZE(devices)); + imx31_add_imx_i2c1(NULL); /* Register UART */ - mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_uart_device1, &uart_pdata); + imx31_add_imx_uart0(&uart_pdata); + imx31_add_imx_uart1(&uart_pdata); /* SMSC9118 IRQ pin */ gpio_direction_input(MX31_PIN_GPIO1_0); @@ -532,7 +531,7 @@ static void __init armadillo5x0_init(void) &armadillo5x0_nor_flash_pdata); /* Register NAND Flash */ - mxc_register_device(&mxc_nand_device, &armadillo5x0_nand_flash_pdata); + imx31_add_mxc_nand(&armadillo5x0_nand_board_info); /* set NAND page size to 2k if not configured via boot mode pins */ __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR); diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c new file mode 100644 index 00000000000..63f970f340a --- /dev/null +++ b/arch/arm/mach-mx3/mach-cpuimx35.c @@ -0,0 +1,227 @@ +/* + * Copyright (C) 2010 Eric Benard - eric@eukrea.com + * Copyright (C) 2009 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/types.h> +#include <linux/init.h> + +#include <linux/platform_device.h> +#include <linux/mtd/physmap.h> +#include <linux/memory.h> +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/i2c/tsc2007.h> +#include <linux/usb/otg.h> +#include <linux/usb/ulpi.h> +#include <linux/fsl_devices.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/mach/map.h> + +#include <mach/eukrea-baseboards.h> +#include <mach/hardware.h> +#include <mach/common.h> +#include <mach/iomux-mx35.h> +#include <mach/mxc_nand.h> +#include <mach/mxc_ehci.h> +#include <mach/ulpi.h> + +#include "devices-imx35.h" +#include "devices.h" + +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static const struct imxi2c_platform_data +eukrea_cpuimx35_i2c0_data __initconst = { + .bitrate = 50000, +}; + +#define TSC2007_IRQGPIO (2 * 32 + 2) +static int ts_get_pendown_state(void) +{ + int val = 0; + gpio_free(TSC2007_IRQGPIO); + gpio_request(TSC2007_IRQGPIO, NULL); + gpio_direction_input(TSC2007_IRQGPIO); + + val = gpio_get_value(TSC2007_IRQGPIO); + + gpio_free(TSC2007_IRQGPIO); + gpio_request(TSC2007_IRQGPIO, NULL); + + return val ? 0 : 1; +} + +static int ts_init(void) +{ + gpio_request(TSC2007_IRQGPIO, NULL); + return 0; +} + +static struct tsc2007_platform_data tsc2007_info = { + .model = 2007, + .x_plate_ohms = 180, + .get_pendown_state = ts_get_pendown_state, + .init_platform_hw = ts_init, +}; + +static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = { + { + I2C_BOARD_INFO("pcf8563", 0x51), + }, { + I2C_BOARD_INFO("tsc2007", 0x48), + .type = "tsc2007", + .platform_data = &tsc2007_info, + .irq = gpio_to_irq(TSC2007_IRQGPIO), + }, +}; + +static struct platform_device *devices[] __initdata = { + &mxc_fec_device, + &imx_wdt_device0, +}; + +static struct pad_desc eukrea_cpuimx35_pads[] = { + /* UART1 */ + MX35_PAD_CTS1__UART1_CTS, + MX35_PAD_RTS1__UART1_RTS, + MX35_PAD_TXD1__UART1_TXD_MUX, + MX35_PAD_RXD1__UART1_RXD_MUX, + /* FEC */ + MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, + MX35_PAD_FEC_RX_DV__FEC_RX_DV, + MX35_PAD_FEC_COL__FEC_COL, + MX35_PAD_FEC_RDATA0__FEC_RDATA_0, + MX35_PAD_FEC_TDATA0__FEC_TDATA_0, + MX35_PAD_FEC_TX_EN__FEC_TX_EN, + MX35_PAD_FEC_MDC__FEC_MDC, + MX35_PAD_FEC_MDIO__FEC_MDIO, + MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, + MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, + MX35_PAD_FEC_CRS__FEC_CRS, + MX35_PAD_FEC_RDATA1__FEC_RDATA_1, + MX35_PAD_FEC_TDATA1__FEC_TDATA_1, + MX35_PAD_FEC_RDATA2__FEC_RDATA_2, + MX35_PAD_FEC_TDATA2__FEC_TDATA_2, + MX35_PAD_FEC_RDATA3__FEC_RDATA_3, + MX35_PAD_FEC_TDATA3__FEC_TDATA_3, + /* I2C1 */ + MX35_PAD_I2C1_CLK__I2C1_SCL, + MX35_PAD_I2C1_DAT__I2C1_SDA, + /* TSC2007 IRQ */ + MX35_PAD_ATA_DA2__GPIO3_2, +}; + +static const struct mxc_nand_platform_data +eukrea_cpuimx35_nand_board_info __initconst = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + +static struct mxc_usbh_platform_data otg_pdata = { + .portsc = MXC_EHCI_MODE_UTMI, + .flags = MXC_EHCI_INTERFACE_DIFF_UNI, +}; + +static struct mxc_usbh_platform_data usbh1_pdata = { + .portsc = MXC_EHCI_MODE_SERIAL, + .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | + MXC_EHCI_IPPUE_DOWN, +}; + +static struct fsl_usb2_platform_data otg_device_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_UTMI, +}; + +static int otg_mode_host; + +static int __init eukrea_cpuimx35_otg_mode(char *options) +{ + if (!strcmp(options, "host")) + otg_mode_host = 1; + else if (!strcmp(options, "device")) + otg_mode_host = 0; + else + pr_info("otg_mode neither \"host\" nor \"device\". " + "Defaulting to device\n"); + return 0; +} +__setup("otg_mode=", eukrea_cpuimx35_otg_mode); + +/* + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads, + ARRAY_SIZE(eukrea_cpuimx35_pads)); + + platform_add_devices(devices, ARRAY_SIZE(devices)); + + imx35_add_imx_uart0(&uart_pdata); + imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info); + + i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices, + ARRAY_SIZE(eukrea_cpuimx35_i2c_devices)); + imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data); + +#if defined(CONFIG_USB_ULPI) + if (otg_mode_host) { + otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_otg_host, &otg_pdata); + } + mxc_register_device(&mxc_usbh1, &usbh1_pdata); +#endif + if (!otg_mode_host) + mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + +#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD + eukrea_mbimxsd_baseboard_init(); +#endif +} + +static void __init eukrea_cpuimx35_timer_init(void) +{ + mx35_clocks_init(); +} + +struct sys_timer eukrea_cpuimx35_timer = { + .init = eukrea_cpuimx35_timer_init, +}; + +MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35") + /* Maintainer: Eukrea Electromatique */ + .phys_io = MX35_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = MX3x_PHYS_OFFSET + 0x100, + .map_io = mx35_map_io, + .init_irq = mx35_init_irq, + .init_machine = mxc_board_init, + .timer = &eukrea_cpuimx35_timer, +MACHINE_END diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c index f085d5d1a6d..5b23e416d6c 100644 --- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c +++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c @@ -16,10 +16,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/gpio.h> @@ -37,13 +33,12 @@ #include <asm/mach/map.h> #include <asm/mach/time.h> -#include <mach/board-kzmarm11.h> #include <mach/clock.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> #include <mach/memory.h> +#include "devices-imx31.h" #include "devices.h" #define KZM_ARM11_IO_ADDRESS(x) ( \ @@ -51,6 +46,23 @@ IMX_IO_ADDRESS(x, MX31_CS5) ?: \ MX31_IO_ADDRESS(x)) +/* + * KZM-ARM11-01 Board Control Registers on FPGA + */ +#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000) +#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001) +#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002) +#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004) +#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008) +#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010) +#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020) +#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003) + +/* + * External UART for touch panel on FPGA + */ +#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050) + #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) /* * KZM-ARM11-01 has an external UART on FPGA @@ -173,15 +185,14 @@ static inline int kzm_init_smsc9118(void) #endif #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; static void __init kzm_init_imx_uart(void) { - mxc_register_device(&mxc_uart_device0, &uart_pdata); - - mxc_register_device(&mxc_uart_device1, &uart_pdata); + imx31_add_imx_uart0(&uart_pdata); + imx31_add_imx_uart1(&uart_pdata); } #else static inline void kzm_init_imx_uart(void) diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index 58e57291b79..6fe69e124d3 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -10,10 +10,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/delay.h> @@ -22,7 +18,6 @@ #include <linux/clk.h> #include <linux/irq.h> #include <linux/gpio.h> -#include <linux/smsc911x.h> #include <linux/platform_device.h> #include <linux/mfd/mc13783.h> #include <linux/spi/spi.h> @@ -37,19 +32,47 @@ #include <asm/memory.h> #include <asm/mach/map.h> #include <mach/common.h> -#include <mach/board-mx31_3ds.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> -#include <mach/mxc_nand.h> -#include <mach/spi.h> +#include <mach/3ds_debugboard.h> + +#include "devices-imx31.h" #include "devices.h" -/*! - * @file mx31_3ds.c - * - * @brief This file contains the board-specific initialization routines. - * - * @ingroup System +/* Definitions for components on the Debug board */ + +/* Base address of CPLD controller on the Debug board */ +#define DEBUG_BASE_ADDRESS CS5_IO_ADDRESS(MX3x_CS5_BASE_ADDR) + +/* LAN9217 ethernet base address */ +#define LAN9217_BASE_ADDR MX3x_CS5_BASE_ADDR + +/* CPLD config and interrupt base address */ +#define CPLD_ADDR (DEBUG_BASE_ADDRESS + 0x20000) + +/* status, interrupt */ +#define CPLD_INT_STATUS_REG (CPLD_ADDR + 0x10) +#define CPLD_INT_MASK_REG (CPLD_ADDR + 0x38) +#define CPLD_INT_RESET_REG (CPLD_ADDR + 0x20) +/* magic word for debug CPLD */ +#define CPLD_MAGIC_NUMBER1_REG (CPLD_ADDR + 0x40) +#define CPLD_MAGIC_NUMBER2_REG (CPLD_ADDR + 0x48) +/* CPLD code version */ +#define CPLD_CODE_VER_REG (CPLD_ADDR + 0x50) +/* magic word for debug CPLD */ +#define CPLD_MAGIC_NUMBER3_REG (CPLD_ADDR + 0x58) + +/* CPLD IRQ line for external uart, external ethernet etc */ +#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1) + +#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) +#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) + +#define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0) + +#define MXC_MAX_EXP_IO_LINES 16 + +/* + * This file contains the board-specific initialization routines. */ static int mx31_3ds_pins[] = { @@ -145,7 +168,7 @@ static int spi1_internal_chipselect[] = { MXC_SPI_CS(2), }; -static struct spi_imx_master spi1_pdata = { +static const struct spi_imx_master spi1_pdata __initconst = { .chipselect = spi1_internal_chipselect, .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect), }; @@ -165,7 +188,8 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = { /* * NAND Flash */ -static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = { +static const struct mxc_nand_platform_data +mx31_3ds_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, #ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT @@ -182,8 +206,10 @@ static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = { #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR) -static void mx31_3ds_usbotg_init(void) +static int mx31_3ds_usbotg_init(void) { + int err; + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); @@ -197,10 +223,25 @@ static void mx31_3ds_usbotg_init(void) mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); - gpio_request(USBOTG_RST_B, "otgusb-reset"); - gpio_direction_output(USBOTG_RST_B, 0); + err = gpio_request(USBOTG_RST_B, "otgusb-reset"); + if (err) { + pr_err("Failed to request the USB OTG reset gpio\n"); + return err; + } + + err = gpio_direction_output(USBOTG_RST_B, 0); + if (err) { + pr_err("Failed to drive the USB OTG reset gpio\n"); + goto usbotg_free_reset; + } + mdelay(1); gpio_set_value(USBOTG_RST_B, 1); + return 0; + +usbotg_free_reset: + gpio_free(USBOTG_RST_B); + return err; } static struct fsl_usb2_platform_data usbotg_pdata = { @@ -208,178 +249,16 @@ static struct fsl_usb2_platform_data usbotg_pdata = { .phy_mode = FSL_USB2_PHY_ULPI, }; -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; /* - * Support for the SMSC9217 on the Debug board. - */ - -static struct smsc911x_platform_config smsc911x_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, - .phy_interface = PHY_INTERFACE_MODE_MII, -}; - -static struct resource smsc911x_resources[] = { - { - .start = LAN9217_BASE_ADDR, - .end = LAN9217_BASE_ADDR + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = EXPIO_INT_ENET, - .end = EXPIO_INT_ENET, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smsc911x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_config, - }, -}; - -/* - * Routines for the CPLD on the debug board. It contains a CPLD handling - * LEDs, switches, interrupts for Ethernet. - */ - -static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc) -{ - uint32_t imr_val; - uint32_t int_valid; - uint32_t expio_irq; - - imr_val = __raw_readw(CPLD_INT_MASK_REG); - int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val; - - expio_irq = MXC_EXP_IO_BASE; - for (; int_valid != 0; int_valid >>= 1, expio_irq++) { - if ((int_valid & 1) == 0) - continue; - generic_handle_irq(expio_irq); - } -} - -/* - * Disable an expio pin's interrupt by setting the bit in the imr. - * @param irq an expio virtual irq number - */ -static void expio_mask_irq(uint32_t irq) -{ - uint16_t reg; - uint32_t expio = MXC_IRQ_TO_EXPIO(irq); - - /* mask the interrupt */ - reg = __raw_readw(CPLD_INT_MASK_REG); - reg |= 1 << expio; - __raw_writew(reg, CPLD_INT_MASK_REG); -} - -/* - * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. - * @param irq an expanded io virtual irq number - */ -static void expio_ack_irq(uint32_t irq) -{ - uint32_t expio = MXC_IRQ_TO_EXPIO(irq); - - /* clear the interrupt status */ - __raw_writew(1 << expio, CPLD_INT_RESET_REG); - __raw_writew(0, CPLD_INT_RESET_REG); - /* mask the interrupt */ - expio_mask_irq(irq); -} - -/* - * Enable a expio pin's interrupt by clearing the bit in the imr. - * @param irq a expio virtual irq number - */ -static void expio_unmask_irq(uint32_t irq) -{ - uint16_t reg; - uint32_t expio = MXC_IRQ_TO_EXPIO(irq); - - /* unmask the interrupt */ - reg = __raw_readw(CPLD_INT_MASK_REG); - reg &= ~(1 << expio); - __raw_writew(reg, CPLD_INT_MASK_REG); -} - -static struct irq_chip expio_irq_chip = { - .ack = expio_ack_irq, - .mask = expio_mask_irq, - .unmask = expio_unmask_irq, -}; - -static int __init mx31_3ds_init_expio(void) -{ - int i; - int ret; - - /* Check if there's a debug board connected */ - if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) || - (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) || - (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) { - /* No Debug board found */ - return -ENODEV; - } - - pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n", - __raw_readw(CPLD_CODE_VER_REG)); - - /* - * Configure INT line as GPIO input - */ - ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq"); - if (ret) - pr_warning("could not get LAN irq gpio\n"); - else - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); - - /* Disable the interrupts and clear the status */ - __raw_writew(0, CPLD_INT_MASK_REG); - __raw_writew(0xFFFF, CPLD_INT_RESET_REG); - __raw_writew(0, CPLD_INT_RESET_REG); - __raw_writew(0x1F, CPLD_INT_MASK_REG); - for (i = MXC_EXP_IO_BASE; - i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); - i++) { - set_irq_chip(i, &expio_irq_chip); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } - set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW); - set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler); - - return 0; -} - -/* - * This structure defines the MX31 memory map. - */ -static struct map_desc mx31_3ds_io_desc[] __initdata = { - { - .virtual = MX31_CS5_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR), - .length = MX31_CS5_SIZE, - .type = MT_DEVICE, - }, -}; - -/* * Set up static virtual mappings. */ static void __init mx31_3ds_map_io(void) { mx31_map_io(); - iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc)); } /*! @@ -390,10 +269,10 @@ static void __init mxc_board_init(void) mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), "mx31_3ds"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata); + imx31_add_imx_uart0(&uart_pdata); + imx31_add_mxc_nand(&mx31_3ds_nand_board_info); - mxc_register_device(&mxc_spi_device1, &spi1_pdata); + imx31_add_spi_imx0(&spi1_pdata); spi_register_board_info(mx31_3ds_spi_devs, ARRAY_SIZE(mx31_3ds_spi_devs)); @@ -402,8 +281,9 @@ static void __init mxc_board_init(void) mx31_3ds_usbotg_init(); mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata); - if (!mx31_3ds_init_expio()) - platform_device_register(&smsc911x_device); + if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT)) + printk(KERN_WARNING "Init of the debugboard failed, all " + "devices on the board are unusable.\n"); } static void __init mx31_3ds_timer_init(void) diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c index b3d1a1895c2..94b3e7c4240 100644 --- a/arch/arm/mach-mx3/mach-mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/types.h> @@ -33,8 +29,6 @@ #include <asm/memory.h> #include <asm/mach/map.h> #include <mach/common.h> -#include <mach/board-mx31ads.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 @@ -43,14 +37,45 @@ #include <linux/mfd/wm8350/pmic.h> #endif +#include "devices-imx31.h" #include "devices.h" -/*! - * @file mx31ads.c - * - * @brief This file contains the board-specific initialization routines. - * - * @ingroup System +/* Base address of PBC controller */ +#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT +/* Offsets for the PBC Controller register */ + +/* PBC Board interrupt status register */ +#define PBC_INTSTATUS 0x000016 + +/* PBC Board interrupt current status register */ +#define PBC_INTCURR_STATUS 0x000018 + +/* PBC Interrupt mask register set address */ +#define PBC_INTMASK_SET 0x00001A + +/* PBC Interrupt mask register clear address */ +#define PBC_INTMASK_CLEAR 0x00001C + +/* External UART A */ +#define PBC_SC16C652_UARTA 0x010000 + +/* External UART B */ +#define PBC_SC16C652_UARTB 0x010010 + +#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) +#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS) +#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) +#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4) + +#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) +#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) + +#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) +#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11) + +#define MXC_MAX_EXP_IO_LINES 16 +/* + * This file contains the board-specific initialization routines. */ #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) @@ -98,7 +123,7 @@ static inline int mxc_init_extuart(void) #endif #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -112,7 +137,7 @@ static unsigned int uart_pins[] = { static inline void mxc_init_imx_uart(void) { mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); + imx31_add_imx_uart0(&uart_pdata); } #else /* !SERIAL_IMX */ static inline void mxc_init_imx_uart(void) @@ -475,7 +500,7 @@ static void mxc_init_i2c(void) mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)); mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)); - mxc_register_device(&mxc_i2c_device1, NULL); + imx31_add_imx_i2c1(NULL); } #else static void mxc_init_i2c(void) diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c index b2c7f512070..8f66f65e80e 100644 --- a/arch/arm/mach-mx3/mach-mx31lilly.c +++ b/arch/arm/mach-mx3/mach-mx31lilly.c @@ -18,10 +18,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/types.h> @@ -46,10 +42,10 @@ #include <mach/common.h> #include <mach/iomux-mx3.h> #include <mach/board-mx31lilly.h> -#include <mach/spi.h> #include <mach/mxc_ehci.h> #include <mach/ulpi.h> +#include "devices-imx31.h" #include "devices.h" /* @@ -269,12 +265,12 @@ static int spi_internal_chipselect[] = { MXC_SPI_CS(2), }; -static struct spi_imx_master spi0_pdata = { +static const struct spi_imx_master spi0_pdata __initconst = { .chipselect = spi_internal_chipselect, .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), }; -static struct spi_imx_master spi1_pdata = { +static const struct spi_imx_master spi1_pdata __initconst = { .chipselect = spi_internal_chipselect, .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), }; @@ -289,6 +285,7 @@ static struct spi_board_info mc13783_dev __initdata = { .bus_num = 1, .chip_select = 0, .platform_data = &mc13783_pdata, + .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), }; static struct platform_device *devices[] __initdata = { @@ -331,8 +328,8 @@ static void __init mx31lilly_board_init(void) mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1"); mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2"); - mxc_register_device(&mxc_spi_device0, &spi0_pdata); - mxc_register_device(&mxc_spi_device1, &spi1_pdata); + imx31_add_spi_imx0(&spi0_pdata); + imx31_add_spi_imx1(&spi1_pdata); spi_register_board_info(&mc13783_dev, 1); platform_add_devices(devices, ARRAY_SIZE(devices)); diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c index 2b6d1140087..da236c497d2 100644 --- a/arch/arm/mach-mx3/mach-mx31lite.c +++ b/arch/arm/mach-mx3/mach-mx31lite.c @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/types.h> @@ -42,14 +38,12 @@ #include <mach/hardware.h> #include <mach/common.h> #include <mach/board-mx31lite.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> #include <mach/irqs.h> -#include <mach/mxc_nand.h> -#include <mach/spi.h> #include <mach/mxc_ehci.h> #include <mach/ulpi.h> +#include "devices-imx31.h" #include "devices.h" /* @@ -69,7 +63,8 @@ static unsigned int mx31lite_pins[] = { MX31_PIN_CSPI2_SS2__SS2, }; -static struct mxc_nand_platform_data mx31lite_nand_board_info = { +static const struct mxc_nand_platform_data +mx31lite_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, }; @@ -112,7 +107,7 @@ static int spi_internal_chipselect[] = { MXC_SPI_CS(0), }; -static struct spi_imx_master spi1_pdata = { +static const struct spi_imx_master spi1_pdata __initconst = { .chipselect = spi_internal_chipselect, .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), }; @@ -253,9 +248,9 @@ static void __init mxc_board_init(void) /* NOR and NAND flash */ platform_device_register(&physmap_flash_device); - mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info); + imx31_add_mxc_nand(&mx31lite_nand_board_info); - mxc_register_device(&mxc_spi_device1, &spi1_pdata); + imx31_add_spi_imx1(&spi1_pdata); spi_register_board_info(&mc13783_spi_dev, 1); #if defined(CONFIG_USB_ULPI) diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c index 62b5e40165d..67776bc61c3 100644 --- a/arch/arm/mach-mx3/mach-mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c @@ -10,10 +10,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/delay.h> @@ -42,16 +38,15 @@ #include <mach/board-mx31moboard.h> #include <mach/common.h> #include <mach/hardware.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> #include <mach/ipu.h> -#include <mach/i2c.h> #include <mach/mmc.h> #include <mach/mxc_ehci.h> #include <mach/mx3_camera.h> #include <mach/spi.h> #include <mach/ulpi.h> +#include "devices-imx31.h" #include "devices.h" static unsigned int moboard_pins[] = { @@ -130,24 +125,36 @@ static struct platform_device mx31moboard_flash = { static int moboard_uart0_init(struct platform_device *pdev) { - gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack"); - gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0); - return 0; + int ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack"); + if (ret) + return ret; + + ret = gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0); + if (ret) + gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1)); + + return ret; +} + +static void moboard_uart0_exit(struct platform_device *pdev) +{ + gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1)); } -static struct imxuart_platform_data uart0_pdata = { +static const struct imxuart_platform_data uart0_pdata __initconst = { .init = moboard_uart0_init, + .exit = moboard_uart0_exit, }; -static struct imxuart_platform_data uart4_pdata = { +static const struct imxuart_platform_data uart4_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; -static struct imxi2c_platform_data moboard_i2c0_pdata = { +static const struct imxi2c_platform_data moboard_i2c0_data __initconst = { .bitrate = 400000, }; -static struct imxi2c_platform_data moboard_i2c1_pdata = { +static const struct imxi2c_platform_data moboard_i2c1_data __initconst = { .bitrate = 100000, }; @@ -156,7 +163,7 @@ static int moboard_spi1_cs[] = { MXC_SPI_CS(2), }; -static struct spi_imx_master moboard_spi1_master = { +static const struct spi_imx_master moboard_spi1_pdata __initconst = { .chipselect = moboard_spi1_cs, .num_chipselect = ARRAY_SIZE(moboard_spi1_cs), }; @@ -286,7 +293,7 @@ static int moboard_spi2_cs[] = { MXC_SPI_CS(1), }; -static struct spi_imx_master moboard_spi2_master = { +static const struct spi_imx_master moboard_spi2_pdata __initconst = { .chipselect = moboard_spi2_cs, .num_chipselect = ARRAY_SIZE(moboard_spi2_cs), }; @@ -499,15 +506,14 @@ static void __init mxc_board_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); - mxc_register_device(&mxc_uart_device0, &uart0_pdata); - - mxc_register_device(&mxc_uart_device4, &uart4_pdata); + imx31_add_imx_uart0(&uart0_pdata); + imx31_add_imx_uart4(&uart4_pdata); - mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata); - mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata); + imx31_add_imx_i2c0(&moboard_i2c0_data); + imx31_add_imx_i2c1(&moboard_i2c1_data); - mxc_register_device(&mxc_spi_device1, &moboard_spi1_master); - mxc_register_device(&mxc_spi_device2, &moboard_spi2_master); + imx31_add_spi_imx1(&moboard_spi1_pdata); + imx31_add_spi_imx2(&moboard_spi2_pdata); gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq"); gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); diff --git a/arch/arm/mach-mx3/mach-mx35pdk.c b/arch/arm/mach-mx3/mach-mx35_3ds.c index bcac84d4dca..1c30d7212f1 100644 --- a/arch/arm/mach-mx3/mach-mx35pdk.c +++ b/arch/arm/mach-mx3/mach-mx35_3ds.c @@ -12,10 +12,12 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * This machine is known as: + * - i.MX35 3-Stack Development System + * - i.MX35 Platform Development Kit (i.MX35 PDK) */ #include <linux/types.h> @@ -32,12 +34,12 @@ #include <mach/hardware.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx35.h> +#include "devices-imx35.h" #include "devices.h" -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -90,7 +92,7 @@ static void __init mxc_board_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); - mxc_register_device(&mxc_uart_device0, &uart_pdata); + imx35_add_imx_uart0(&uart_pdata); mxc_register_device(&mxc_otg_udc_device, &usb_pdata); } diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c index cce41066238..8a292dd1a71 100644 --- a/arch/arm/mach-mx3/mach-pcm037.c +++ b/arch/arm/mach-mx3/mach-pcm037.c @@ -10,10 +10,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/types.h> @@ -43,20 +39,17 @@ #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/mach/map.h> -#include <mach/board-pcm037.h> #include <mach/common.h> #include <mach/hardware.h> -#include <mach/i2c.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> #include <mach/ipu.h> #include <mach/mmc.h> #include <mach/mx3_camera.h> #include <mach/mx3fb.h> -#include <mach/mxc_nand.h> #include <mach/mxc_ehci.h> #include <mach/ulpi.h> +#include "devices-imx31.h" #include "devices.h" #include "pcm037.h" @@ -225,7 +218,7 @@ static struct platform_device pcm037_flash = { .num_resources = 1, }; -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -279,16 +272,17 @@ static struct platform_device pcm037_sram_device = { .resource = &pcm038_sram_resource, }; -static struct mxc_nand_platform_data pcm037_nand_board_info = { +static const struct mxc_nand_platform_data +pcm037_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, }; -static struct imxi2c_platform_data pcm037_i2c_1_data = { +static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = { .bitrate = 100000, }; -static struct imxi2c_platform_data pcm037_i2c_2_data = { +static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = { .bitrate = 20000, }; @@ -545,6 +539,7 @@ static struct platform_device pcm970_sja1000 = { .num_resources = ARRAY_SIZE(pcm970_sja1000_resources), }; +#if defined(CONFIG_USB_ULPI) static struct mxc_usbh_platform_data otg_pdata = { .portsc = MXC_EHCI_MODE_ULPI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, @@ -554,6 +549,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = { .portsc = MXC_EHCI_MODE_ULPI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; +#endif static struct fsl_usb2_platform_data otg_device_pdata = { .operating_mode = FSL_USB2_DR_DEVICE, @@ -581,7 +577,6 @@ __setup("otg_mode=", pcm037_otg_mode); static void __init mxc_board_init(void) { int ret; - u32 tmp; mxc_iomux_set_gpr(MUX_PGP_UH2, 1); @@ -614,9 +609,10 @@ static void __init mxc_board_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); - mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_uart_device1, &uart_pdata); - mxc_register_device(&mxc_uart_device2, &uart_pdata); + imx31_add_imx_uart0(&uart_pdata); + /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */ + imx31_add_imx_uart1(&uart_pdata); + imx31_add_imx_uart2(&uart_pdata); mxc_register_device(&mxc_w1_master_device, NULL); @@ -634,10 +630,10 @@ static void __init mxc_board_init(void) i2c_register_board_info(1, pcm037_i2c_devices, ARRAY_SIZE(pcm037_i2c_devices)); - mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data); - mxc_register_device(&mxc_i2c_device2, &pcm037_i2c_2_data); + imx31_add_imx_i2c1(&pcm037_i2c1_data); + imx31_add_imx_i2c2(&pcm037_i2c2_data); - mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); + imx31_add_mxc_nand(&pcm037_nand_board_info); mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); mxc_register_device(&mx3_ipu, &mx3_ipu_data); mxc_register_device(&mx3_fb, &mx3fb_pdata); diff --git a/arch/arm/mach-mx3/mach-pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c index 8d386000fc4..c8b98218efe 100644 --- a/arch/arm/mach-mx3/mach-pcm037_eet.c +++ b/arch/arm/mach-mx3/mach-pcm037_eet.c @@ -13,9 +13,6 @@ #include <linux/spi/spi.h> #include <mach/common.h> -#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) -#include <mach/spi.h> -#endif #include <mach/iomux-mx3.h> #include <asm/mach-types.h> @@ -64,7 +61,7 @@ static struct spi_board_info pcm037_spi_dev[] = { #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) static int pcm037_spi1_cs[] = {MXC_SPI_CS(1), IOMUX_TO_GPIO(MX31_PIN_KEY_COL7)}; -struct spi_imx_master pcm037_spi1_master = { +static const struct spi_imx_master pcm037_spi1_pdata __initconst = { .chipselect = pcm037_spi1_cs, .num_chipselect = ARRAY_SIZE(pcm037_spi1_cs), }; @@ -184,7 +181,7 @@ static int eet_init_devices(void) /* SPI */ spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev)); #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) - mxc_register_device(&mxc_spi_device0, &pcm037_spi1_master); + imx35_add_spi_imx0(&pcm037_spi1_pdata); #endif platform_device_register(&pcm037_gpio_keys_device); diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index 78d9185a9d4..47f5311b301 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c @@ -10,10 +10,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/types.h> @@ -40,19 +36,15 @@ #include <mach/hardware.h> #include <mach/common.h> -#include <mach/imx-uart.h> -#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE -#include <mach/i2c.h> -#endif #include <mach/iomux-mx35.h> #include <mach/ipu.h> #include <mach/mx3fb.h> -#include <mach/mxc_nand.h> #include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include <mach/audmux.h> #include <mach/ssi.h> +#include "devices-imx35.h" #include "devices.h" static const struct fb_videomode fb_modedb[] = { @@ -122,12 +114,12 @@ static struct platform_device pcm043_flash = { .num_resources = 1, }; -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE -static struct imxi2c_platform_data pcm043_i2c_1_data = { +static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = { .bitrate = 50000, }; @@ -222,6 +214,9 @@ static struct pad_desc pcm043_pads[] = { MX35_PAD_STXD4__AUDMUX_AUD4_TXD, MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, MX35_PAD_SCK4__AUDMUX_AUD4_TXC, + /* CAN2 */ + MX35_PAD_TX5_RX0__CAN2_TXCAN, + MX35_PAD_TX4_RX1__CAN2_RXCAN, }; #define AC97_GPIO_TXFS (1 * 32 + 31) @@ -304,11 +299,13 @@ static struct imx_ssi_platform_data pcm043_ssi_pdata = { .flags = IMX_SSI_USE_AC97, }; -static struct mxc_nand_platform_data pcm037_nand_board_info = { +static const struct mxc_nand_platform_data +pcm037_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, }; +#if defined(CONFIG_USB_ULPI) static struct mxc_usbh_platform_data otg_pdata = { .portsc = MXC_EHCI_MODE_UTMI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, @@ -319,6 +316,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = { .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN, }; +#endif static struct fsl_usb2_platform_data otg_device_pdata = { .operating_mode = FSL_USB2_DR_DEVICE, @@ -361,17 +359,17 @@ static void __init mxc_board_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); - mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); + imx35_add_imx_uart0(&uart_pdata); + imx35_add_mxc_nand(&pcm037_nand_board_info); mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata); - mxc_register_device(&mxc_uart_device1, &uart_pdata); + imx35_add_imx_uart1(&uart_pdata); #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE i2c_register_board_info(0, pcm043_i2c_devices, ARRAY_SIZE(pcm043_i2c_devices)); - mxc_register_device(&mxc_i2c_device0, &pcm043_i2c_1_data); + imx35_add_imx_i2c0(&pcm043_i2c0_data); #endif mxc_register_device(&mx3_ipu, &mx3_ipu_data); @@ -390,6 +388,7 @@ static void __init mxc_board_init(void) if (!otg_mode_host) mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + imx35_add_flexcan1(NULL); } static void __init pcm043_timer_init(void) diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c index e5b5b8323a1..d44ac70222a 100644 --- a/arch/arm/mach-mx3/mach-qong.c +++ b/arch/arm/mach-mx3/mach-qong.c @@ -10,10 +10,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/types.h> @@ -34,9 +30,9 @@ #include <mach/common.h> #include <asm/page.h> #include <asm/setup.h> -#include <mach/board-qong.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> + +#include "devices-imx31.h" #include "devices.h" /* FPGA defines */ @@ -62,7 +58,7 @@ * This file contains the board-specific initialization routines. */ -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -73,11 +69,11 @@ static int uart_pins[] = { MX31_PIN_RXD1__RXD1 }; -static inline void mxc_init_imx_uart(void) +static inline void __init mxc_init_imx_uart(void) { mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); + imx31_add_imx_uart0(&uart_pdata); } static struct resource dnet_resources[] = { @@ -116,7 +112,7 @@ static struct physmap_flash_data qong_flash_data = { static struct resource qong_flash_resource = { .start = MX31_CS0_BASE_ADDR, - .end = MX31_CS0_BASE_ADDR + QONG_NOR_SIZE - 1, + .end = MX31_CS0_BASE_ADDR + SZ_128M - 1, .flags = IORESOURCE_MEM, }; diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c index 6858a4f9806..20e48c0195c 100644 --- a/arch/arm/mach-mx3/mm.c +++ b/arch/arm/mach-mx3/mm.c @@ -14,10 +14,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/mm.h> @@ -97,9 +93,12 @@ void __init mx35_map_io(void) } #endif +int imx3x_register_gpios(void); + void __init mx31_init_irq(void) { mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR)); + imx3x_register_gpios(); } void __init mx35_init_irq(void) diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c index 7aebd74a12e..827fd3c8020 100644 --- a/arch/arm/mach-mx3/mx31lilly-db.c +++ b/arch/arm/mach-mx3/mx31lilly-db.c @@ -18,10 +18,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/kernel.h> @@ -36,13 +32,13 @@ #include <mach/hardware.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> #include <mach/board-mx31lilly.h> #include <mach/mmc.h> #include <mach/mx3fb.h> #include <mach/ipu.h> +#include "devices-imx31.h" #include "devices.h" /* @@ -96,7 +92,7 @@ static unsigned int lilly_db_board_pins[] __initdata = { }; /* UART */ -static struct imxuart_platform_data uart_pdata __initdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -217,9 +213,9 @@ void __init mx31lilly_db_init(void) mxc_iomux_setup_multiple_pins(lilly_db_board_pins, ARRAY_SIZE(lilly_db_board_pins), "development board pins"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_uart_device1, &uart_pdata); - mxc_register_device(&mxc_uart_device2, &uart_pdata); + imx31_add_imx_uart0(&uart_pdata); + imx31_add_imx_uart1(&uart_pdata); + imx31_add_imx_uart2(&uart_pdata); mxc_register_device(&mxcsdhc_device0, &mmc_pdata); mx31lilly_init_fb(); } diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c index 5f05bfbec38..7b0e74e275b 100644 --- a/arch/arm/mach-mx3/mx31lite-db.c +++ b/arch/arm/mach-mx3/mx31lite-db.c @@ -18,10 +18,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/kernel.h> @@ -37,12 +33,11 @@ #include <mach/hardware.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> #include <mach/board-mx31lite.h> #include <mach/mmc.h> -#include <mach/spi.h> +#include "devices-imx31.h" #include "devices.h" /* @@ -76,7 +71,7 @@ static unsigned int litekit_db_board_pins[] __initdata = { }; /* UART */ -static struct imxuart_platform_data uart_pdata __initdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -161,7 +156,7 @@ static int spi_internal_chipselect[] = { MXC_SPI_CS(2), }; -static struct spi_imx_master spi0_pdata = { +static const struct spi_imx_master spi0_pdata __initconst = { .chipselect = spi_internal_chipselect, .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), }; @@ -201,9 +196,9 @@ void __init mx31lite_db_init(void) mxc_iomux_setup_multiple_pins(litekit_db_board_pins, ARRAY_SIZE(litekit_db_board_pins), "development board pins"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); + imx31_add_imx_uart0(&uart_pdata); mxc_register_device(&mxcsdhc_device0, &mmc_pdata); - mxc_register_device(&mxc_spi_device0, &spi0_pdata); + imx31_add_spi_imx0(&spi0_pdata); platform_device_register(&litekit_led_device); mxc_register_device(&imx_wdt_device0, NULL); mxc_register_device(&imx_rtc_device0, NULL); diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c index 582299cb2c0..fc395a7a859 100644 --- a/arch/arm/mach-mx3/mx31moboard-devboard.c +++ b/arch/arm/mach-mx3/mx31moboard-devboard.c @@ -10,10 +10,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/gpio.h> @@ -27,13 +23,13 @@ #include <linux/usb/otg.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> #include <mach/hardware.h> #include <mach/mmc.h> #include <mach/mxc_ehci.h> #include <mach/ulpi.h> +#include "devices-imx31.h" #include "devices.h" static unsigned int devboard_pins[] = { @@ -56,7 +52,7 @@ static unsigned int devboard_pins[] = { MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, }; -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -230,7 +226,7 @@ void __init mx31moboard_devboard_init(void) mxc_iomux_setup_multiple_pins(devboard_pins, ARRAY_SIZE(devboard_pins), "devboard"); - mxc_register_device(&mxc_uart_device1, &uart_pdata); + imx31_add_imx_uart1(&uart_pdata); mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c index 4930f8c27e6..0551eb39d97 100644 --- a/arch/arm/mach-mx3/mx31moboard-marxbot.c +++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c @@ -10,10 +10,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/delay.h> diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c index 293eea6d9d9..40c3e7564cb 100644 --- a/arch/arm/mach-mx3/mx31moboard-smartbot.c +++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c @@ -10,10 +10,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/delay.h> @@ -30,7 +26,6 @@ #include <mach/common.h> #include <mach/hardware.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> #include <mach/board-mx31moboard.h> #include <mach/mxc_ehci.h> @@ -38,6 +33,7 @@ #include <media/soc_camera.h> +#include "devices-imx31.h" #include "devices.h" static unsigned int smartbot_pins[] = { @@ -59,7 +55,7 @@ static unsigned int smartbot_pins[] = { MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, }; -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -183,8 +179,7 @@ void __init mx31moboard_smartbot_init(int board) mxc_iomux_setup_multiple_pins(smartbot_pins, ARRAY_SIZE(smartbot_pins), "smartbot"); - mxc_register_device(&mxc_uart_device1, &uart_pdata); - + imx31_add_imx_uart1(&uart_pdata); switch (board) { case MX31SMARTBOT: diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 1576d51e676..0848db5dd36 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -15,4 +15,31 @@ config MACH_MX51_BABBAGE u-boot. This includes specific configurations for the board and its peripherals. +config MACH_MX51_3DS + bool "Support MX51PDK (3DS)" + select MXC_DEBUG_BOARD + help + Include support for MX51PDK (3DS) platform. This includes specific + configurations for the board and its peripherals. + +config MACH_EUKREA_CPUIMX51 + bool "Support Eukrea CPUIMX51 module" + help + Include support for Eukrea CPUIMX51 platform. This includes + specific configurations for the module and its peripherals. + +choice + prompt "Baseboard" + depends on MACH_EUKREA_CPUIMX51 + default MACH_EUKREA_MBIMX51_BASEBOARD + +config MACH_EUKREA_MBIMX51_BASEBOARD + prompt "Eukrea MBIMX51 development board" + bool + help + This adds board specific devices that can be found on Eukrea's + MBIMX51 evaluation board. + +endchoice + endif diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index bf23f869ef5..86c66e7f52f 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -6,4 +6,6 @@ obj-y := cpu.o mm.o clock-mx51.o devices.o obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o - +obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o +obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o +obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c new file mode 100644 index 00000000000..623607a20f5 --- /dev/null +++ b/arch/arm/mach-mx5/board-cpuimx51.c @@ -0,0 +1,293 @@ +/* + * + * Copyright (C) 2010 Eric Bénard <eric@eukrea.com> + * + * based on board-mx51_babbage.c which is + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <linux/i2c.h> +#include <linux/gpio.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/fsl_devices.h> + +#include <mach/eukrea-baseboards.h> +#include <mach/common.h> +#include <mach/hardware.h> +#include <mach/imx-uart.h> +#include <mach/iomux-mx51.h> +#include <mach/i2c.h> +#include <mach/mxc_ehci.h> + +#include <asm/irq.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include "devices.h" + +#define CPUIMX51_USBH1_STP (0*32 + 27) +#define CPUIMX51_QUARTA_GPIO (2*32 + 28) +#define CPUIMX51_QUARTB_GPIO (2*32 + 25) +#define CPUIMX51_QUARTC_GPIO (2*32 + 26) +#define CPUIMX51_QUARTD_GPIO (2*32 + 27) +#define CPUIMX51_QUARTA_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO) +#define CPUIMX51_QUARTB_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO) +#define CPUIMX51_QUARTC_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO) +#define CPUIMX51_QUARTD_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTD_GPIO) +#define CPUIMX51_QUART_XTAL 14745600 +#define CPUIMX51_QUART_REGSHIFT 17 + +/* USB_CTRL_1 */ +#define MX51_USB_CTRL_1_OFFSET 0x10 +#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) + +#define MX51_USB_PLLDIV_12_MHZ 0x00 +#define MX51_USB_PLL_DIV_19_2_MHZ 0x01 +#define MX51_USB_PLL_DIV_24_MHZ 0x02 + +#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) +static struct plat_serial8250_port serial_platform_data[] = { + { + .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000), + .irq = CPUIMX51_QUARTA_IRQ, + .irqflags = IRQF_TRIGGER_HIGH, + .uartclk = CPUIMX51_QUART_XTAL, + .regshift = CPUIMX51_QUART_REGSHIFT, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, + }, { + .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000), + .irq = CPUIMX51_QUARTB_IRQ, + .irqflags = IRQF_TRIGGER_HIGH, + .uartclk = CPUIMX51_QUART_XTAL, + .regshift = CPUIMX51_QUART_REGSHIFT, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, + }, { + .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000), + .irq = CPUIMX51_QUARTC_IRQ, + .irqflags = IRQF_TRIGGER_HIGH, + .uartclk = CPUIMX51_QUART_XTAL, + .regshift = CPUIMX51_QUART_REGSHIFT, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, + }, { + .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000), + .irq = CPUIMX51_QUARTD_IRQ, + .irqflags = IRQF_TRIGGER_HIGH, + .uartclk = CPUIMX51_QUART_XTAL, + .regshift = CPUIMX51_QUART_REGSHIFT, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, + }, { + } +}; + +static struct platform_device serial_device = { + .name = "serial8250", + .id = 0, + .dev = { + .platform_data = serial_platform_data, + }, +}; +#endif + +static struct platform_device *devices[] __initdata = { + &mxc_fec_device, +#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) + &serial_device, +#endif +}; + +static struct pad_desc eukrea_cpuimx51_pads[] = { + /* UART1 */ + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, + + /* I2C2 */ + MX51_PAD_GPIO_1_2__I2C2_SCL, + MX51_PAD_GPIO_1_3__I2C2_SDA, + MX51_PAD_NANDF_D10__GPIO_3_30, + + /* QUART IRQ */ + MX51_PAD_NANDF_D15__GPIO_3_25, + MX51_PAD_NANDF_D14__GPIO_3_26, + MX51_PAD_NANDF_D13__GPIO_3_27, + MX51_PAD_NANDF_D12__GPIO_3_28, + + /* USB HOST1 */ + MX51_PAD_USBH1_CLK__USBH1_CLK, + MX51_PAD_USBH1_DIR__USBH1_DIR, + MX51_PAD_USBH1_NXT__USBH1_NXT, + MX51_PAD_USBH1_DATA0__USBH1_DATA0, + MX51_PAD_USBH1_DATA1__USBH1_DATA1, + MX51_PAD_USBH1_DATA2__USBH1_DATA2, + MX51_PAD_USBH1_DATA3__USBH1_DATA3, + MX51_PAD_USBH1_DATA4__USBH1_DATA4, + MX51_PAD_USBH1_DATA5__USBH1_DATA5, + MX51_PAD_USBH1_DATA6__USBH1_DATA6, + MX51_PAD_USBH1_DATA7__USBH1_DATA7, + MX51_PAD_USBH1_STP__USBH1_STP, +}; + +static struct imxuart_platform_data uart_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static struct imxi2c_platform_data eukrea_cpuimx51_i2c_data = { + .bitrate = 100000, +}; + +static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = { + { + I2C_BOARD_INFO("pcf8563", 0x51), + }, +}; + +/* This function is board specific as the bit mask for the plldiv will also +be different for other Freescale SoCs, thus a common bitmask is not +possible and cannot get place in /plat-mxc/ehci.c.*/ +static int initialize_otg_port(struct platform_device *pdev) +{ + u32 v; + void __iomem *usb_base; + void __iomem *usbother_base; + + usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; + + /* Set the PHY clock to 19.2MHz */ + v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); + v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; + v |= MX51_USB_PLL_DIV_19_2_MHZ; + __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); + iounmap(usb_base); + return 0; +} + +static int initialize_usbh1_port(struct platform_device *pdev) +{ + u32 v; + void __iomem *usb_base; + void __iomem *usbother_base; + + usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; + + /* The clock for the USBH1 ULPI port will come externally from the PHY. */ + v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET); + __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET); + iounmap(usb_base); + return 0; +} + +static struct mxc_usbh_platform_data dr_utmi_config = { + .init = initialize_otg_port, + .portsc = MXC_EHCI_UTMI_16BIT, + .flags = MXC_EHCI_INTERNAL_PHY, +}; + +static struct fsl_usb2_platform_data usb_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_UTMI_WIDE, +}; + +static struct mxc_usbh_platform_data usbh1_config = { + .init = initialize_usbh1_port, + .portsc = MXC_EHCI_MODE_ULPI, + .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD), +}; + +static int otg_mode_host; + +static int __init eukrea_cpuimx51_otg_mode(char *options) +{ + if (!strcmp(options, "host")) + otg_mode_host = 1; + else if (!strcmp(options, "device")) + otg_mode_host = 0; + else + pr_info("otg_mode neither \"host\" nor \"device\". " + "Defaulting to device\n"); + return 0; +} +__setup("otg_mode=", eukrea_cpuimx51_otg_mode); + +/* + * Board specific initialization. + */ +static void __init eukrea_cpuimx51_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads, + ARRAY_SIZE(eukrea_cpuimx51_pads)); + + mxc_register_device(&mxc_uart_device0, &uart_pdata); + gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq"); + gpio_direction_input(CPUIMX51_QUARTA_GPIO); + gpio_free(CPUIMX51_QUARTA_GPIO); + gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq"); + gpio_direction_input(CPUIMX51_QUARTB_GPIO); + gpio_free(CPUIMX51_QUARTB_GPIO); + gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq"); + gpio_direction_input(CPUIMX51_QUARTC_GPIO); + gpio_free(CPUIMX51_QUARTC_GPIO); + gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq"); + gpio_direction_input(CPUIMX51_QUARTD_GPIO); + gpio_free(CPUIMX51_QUARTD_GPIO); + + platform_add_devices(devices, ARRAY_SIZE(devices)); + + mxc_register_device(&mxc_i2c_device1, &eukrea_cpuimx51_i2c_data); + i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices, + ARRAY_SIZE(eukrea_cpuimx51_i2c_devices)); + + if (otg_mode_host) + mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); + else { + initialize_otg_port(NULL); + mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata); + } + mxc_register_device(&mxc_usbh1_device, &usbh1_config); + +#ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD + eukrea_mbimx51_baseboard_init(); +#endif +} + +static void __init eukrea_cpuimx51_timer_init(void) +{ + mx51_clocks_init(32768, 24000000, 22579200, 0); +} + +static struct sys_timer mxc_timer = { + .init = eukrea_cpuimx51_timer_init, +}; + +MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module") + /* Maintainer: Eric Bénard <eric@eukrea.com> */ + .phys_io = MX51_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .map_io = mx51_map_io, + .init_irq = mx51_init_irq, + .init_machine = eukrea_cpuimx51_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c new file mode 100644 index 00000000000..f95c2fd9466 --- /dev/null +++ b/arch/arm/mach-mx5/board-mx51_3ds.c @@ -0,0 +1,164 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/irq.h> +#include <linux/platform_device.h> +#include <linux/input/matrix_keypad.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include <mach/hardware.h> +#include <mach/common.h> +#include <mach/iomux-mx51.h> +#include <mach/imx-uart.h> +#include <mach/3ds_debugboard.h> + +#include "devices.h" + +#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 6) + +static struct pad_desc mx51_3ds_pads[] = { + /* UART1 */ + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, + + /* UART2 */ + MX51_PAD_UART2_RXD__UART2_RXD, + MX51_PAD_UART2_TXD__UART2_TXD, + MX51_PAD_EIM_D25__UART2_CTS, + MX51_PAD_EIM_D26__UART2_RTS, + + /* UART3 */ + MX51_PAD_UART3_RXD__UART3_RXD, + MX51_PAD_UART3_TXD__UART3_TXD, + MX51_PAD_EIM_D24__UART3_CTS, + MX51_PAD_EIM_D27__UART3_RTS, + + /* CPLD PARENT IRQ PIN */ + MX51_PAD_GPIO_1_6__GPIO_1_6, + + /* KPP */ + MX51_PAD_KEY_ROW0__KEY_ROW0, + MX51_PAD_KEY_ROW1__KEY_ROW1, + MX51_PAD_KEY_ROW2__KEY_ROW2, + MX51_PAD_KEY_ROW3__KEY_ROW3, + MX51_PAD_KEY_COL0__KEY_COL0, + MX51_PAD_KEY_COL1__KEY_COL1, + MX51_PAD_KEY_COL2__KEY_COL2, + MX51_PAD_KEY_COL3__KEY_COL3, + MX51_PAD_KEY_COL4__KEY_COL4, + MX51_PAD_KEY_COL5__KEY_COL5, +}; + +/* Serial ports */ +#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) +static struct imxuart_platform_data uart_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static inline void mxc_init_imx_uart(void) +{ + mxc_register_device(&mxc_uart_device0, &uart_pdata); + mxc_register_device(&mxc_uart_device1, &uart_pdata); + mxc_register_device(&mxc_uart_device2, &uart_pdata); +} +#else /* !SERIAL_IMX */ +static inline void mxc_init_imx_uart(void) +{ +} +#endif /* SERIAL_IMX */ + +#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE) +static int mx51_3ds_board_keymap[] = { + KEY(0, 0, KEY_1), + KEY(0, 1, KEY_2), + KEY(0, 2, KEY_3), + KEY(0, 3, KEY_F1), + KEY(0, 4, KEY_UP), + KEY(0, 5, KEY_F2), + + KEY(1, 0, KEY_4), + KEY(1, 1, KEY_5), + KEY(1, 2, KEY_6), + KEY(1, 3, KEY_LEFT), + KEY(1, 4, KEY_SELECT), + KEY(1, 5, KEY_RIGHT), + + KEY(2, 0, KEY_7), + KEY(2, 1, KEY_8), + KEY(2, 2, KEY_9), + KEY(2, 3, KEY_F3), + KEY(2, 4, KEY_DOWN), + KEY(2, 5, KEY_F4), + + KEY(3, 0, KEY_0), + KEY(3, 1, KEY_OK), + KEY(3, 2, KEY_ESC), + KEY(3, 3, KEY_ENTER), + KEY(3, 4, KEY_MENU), + KEY(3, 5, KEY_BACK) +}; + +static struct matrix_keymap_data mx51_3ds_map_data = { + .keymap = mx51_3ds_board_keymap, + .keymap_size = ARRAY_SIZE(mx51_3ds_board_keymap), +}; + +static void mxc_init_keypad(void) +{ + mxc_register_device(&mxc_keypad_device, &mx51_3ds_map_data); +} +#else +static inline void mxc_init_keypad(void) +{ +} +#endif + +/* + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads, + ARRAY_SIZE(mx51_3ds_pads)); + mxc_init_imx_uart(); + + if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT)) + printk(KERN_WARNING "Init of the debugboard failed, all " + "devices on the board are unusable.\n"); + + mxc_init_keypad(); +} + +static void __init mx51_3ds_timer_init(void) +{ + mx51_clocks_init(32768, 24000000, 22579200, 0); +} + +static struct sys_timer mxc_timer = { + .init = mx51_3ds_timer_init, +}; + +MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") + /* Maintainer: Freescale Semiconductor, Inc. */ + .phys_io = MX51_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .map_io = mx51_map_io, + .init_irq = mx51_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index ed885f9d7b7..6e384d92e62 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -12,6 +12,7 @@ #include <linux/init.h> #include <linux/platform_device.h> +#include <linux/i2c.h> #include <linux/gpio.h> #include <linux/delay.h> #include <linux/io.h> @@ -21,6 +22,7 @@ #include <mach/hardware.h> #include <mach/imx-uart.h> #include <mach/iomux-mx51.h> +#include <mach/i2c.h> #include <mach/mxc_ehci.h> #include <asm/irq.h> @@ -64,6 +66,18 @@ static struct pad_desc mx51babbage_pads[] = { MX51_PAD_EIM_D27__UART3_RTS, MX51_PAD_EIM_D24__UART3_CTS, + /* I2C1 */ + MX51_PAD_EIM_D16__I2C1_SDA, + MX51_PAD_EIM_D19__I2C1_SCL, + + /* I2C2 */ + MX51_PAD_KEY_COL4__I2C2_SCL, + MX51_PAD_KEY_COL5__I2C2_SDA, + + /* HSI2C */ + MX51_PAD_I2C1_CLK__HSI2C_CLK, + MX51_PAD_I2C1_DAT__HSI2C_DAT, + /* USB HOST1 */ MX51_PAD_USBH1_CLK__USBH1_CLK, MX51_PAD_USBH1_DIR__USBH1_DIR, @@ -78,7 +92,7 @@ static struct pad_desc mx51babbage_pads[] = { MX51_PAD_USBH1_DATA7__USBH1_DATA7, /* USB HUB reset line*/ - MX51_PAD_GPIO_1_7__GPIO1_7, + MX51_PAD_GPIO_1_7__GPIO_1_7, }; /* Serial ports */ @@ -99,6 +113,14 @@ static inline void mxc_init_imx_uart(void) } #endif /* SERIAL_IMX */ +static struct imxi2c_platform_data babbage_i2c_data = { + .bitrate = 100000, +}; + +static struct imxi2c_platform_data babbage_hsi2c_data = { + .bitrate = 400000, +}; + static int gpio_usbh1_active(void) { struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27; @@ -230,6 +252,10 @@ static void __init mxc_board_init(void) mxc_init_imx_uart(); platform_add_devices(devices, ARRAY_SIZE(devices)); + mxc_register_device(&mxc_i2c_device0, &babbage_i2c_data); + mxc_register_device(&mxc_i2c_device1, &babbage_i2c_data); + mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data); + if (otg_mode_host) mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); else { diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c index d9f612d3370..6af69def357 100644 --- a/arch/arm/mach-mx5/clock-mx51.c +++ b/arch/arm/mach-mx5/clock-mx51.c @@ -758,6 +758,10 @@ static struct clk gpt_32k_clk = { .parent = &ckil_clk, }; +static struct clk kpp_clk = { + .id = 0, +}; + #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \ static struct clk name = { \ .id = i, \ @@ -798,6 +802,14 @@ DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET, DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, NULL, NULL, &ipg_clk, NULL); +/* I2C */ +DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET, + NULL, NULL, &ipg_clk, NULL); +DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET, + NULL, NULL, &ipg_clk, NULL); +DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET, + NULL, NULL, &ipg_clk, NULL); + /* FEC */ DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, NULL, NULL, &ipg_clk, NULL); @@ -815,12 +827,16 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) _REGISTER_CLOCK(NULL, "gpt", gpt_clk) _REGISTER_CLOCK("fec.0", NULL, fec_clk) + _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) + _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) + _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk) _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk) _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk) _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk) _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) + _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk) }; static void clk_tree_init(void) diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c index 7130449aacd..1920ff4963b 100644 --- a/arch/arm/mach-mx5/devices.c +++ b/arch/arm/mach-mx5/devices.c @@ -93,6 +93,64 @@ struct platform_device mxc_fec_device = { .resource = mxc_fec_resources, }; +static struct resource mxc_i2c0_resources[] = { + { + .start = MX51_I2C1_BASE_ADDR, + .end = MX51_I2C1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = MX51_MXC_INT_I2C1, + .end = MX51_MXC_INT_I2C1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_i2c_device0 = { + .name = "imx-i2c", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_i2c0_resources), + .resource = mxc_i2c0_resources, +}; + +static struct resource mxc_i2c1_resources[] = { + { + .start = MX51_I2C2_BASE_ADDR, + .end = MX51_I2C2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = MX51_MXC_INT_I2C2, + .end = MX51_MXC_INT_I2C2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_i2c_device1 = { + .name = "imx-i2c", + .id = 1, + .num_resources = ARRAY_SIZE(mxc_i2c1_resources), + .resource = mxc_i2c1_resources, +}; + +static struct resource mxc_hsi2c_resources[] = { + { + .start = MX51_HSI2C_DMA_BASE_ADDR, + .end = MX51_HSI2C_DMA_BASE_ADDR + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MX51_MXC_INT_HS_I2C, + .end = MX51_MXC_INT_HS_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_hsi2c_device = { + .name = "imx-i2c", + .id = 2, + .num_resources = ARRAY_SIZE(mxc_hsi2c_resources), + .resource = mxc_hsi2c_resources +}; + static u64 usb_dma_mask = DMA_BIT_MASK(32); static struct resource usbotg_resources[] = { @@ -168,34 +226,57 @@ struct platform_device mxc_wdt = { .resource = mxc_wdt_resources, }; +static struct resource mxc_kpp_resources[] = { + { + .start = MX51_MXC_INT_KPP, + .end = MX51_MXC_INT_KPP, + .flags = IORESOURCE_IRQ, + } , { + .start = MX51_KPP_BASE_ADDR, + .end = MX51_KPP_BASE_ADDR + 0x8 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device mxc_keypad_device = { + .name = "imx-keypad", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_kpp_resources), + .resource = mxc_kpp_resources, +}; + static struct mxc_gpio_port mxc_gpio_ports[] = { { .chip.label = "gpio-0", .base = MX51_IO_ADDRESS(MX51_GPIO1_BASE_ADDR), .irq = MX51_MXC_INT_GPIO1_LOW, + .irq_high = MX51_MXC_INT_GPIO1_HIGH, .virtual_irq_start = MXC_GPIO_IRQ_START }, { .chip.label = "gpio-1", .base = MX51_IO_ADDRESS(MX51_GPIO2_BASE_ADDR), .irq = MX51_MXC_INT_GPIO2_LOW, + .irq_high = MX51_MXC_INT_GPIO2_HIGH, .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1 }, { .chip.label = "gpio-2", .base = MX51_IO_ADDRESS(MX51_GPIO3_BASE_ADDR), .irq = MX51_MXC_INT_GPIO3_LOW, + .irq_high = MX51_MXC_INT_GPIO3_HIGH, .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2 }, { .chip.label = "gpio-3", .base = MX51_IO_ADDRESS(MX51_GPIO4_BASE_ADDR), .irq = MX51_MXC_INT_GPIO4_LOW, + .irq_high = MX51_MXC_INT_GPIO4_HIGH, .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3 }, }; -int __init mxc_register_gpios(void) +int __init imx51_register_gpios(void) { return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); } diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h index c879ae71cd5..e509cfaad1d 100644 --- a/arch/arm/mach-mx5/devices.h +++ b/arch/arm/mach-mx5/devices.h @@ -6,3 +6,7 @@ extern struct platform_device mxc_usbdr_host_device; extern struct platform_device mxc_usbh1_device; extern struct platform_device mxc_usbdr_udc_device; extern struct platform_device mxc_wdt; +extern struct platform_device mxc_i2c_device0; +extern struct platform_device mxc_i2c_device1; +extern struct platform_device mxc_hsi2c_device; +extern struct platform_device mxc_keypad_device; diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c new file mode 100644 index 00000000000..ffa93d1d6ef --- /dev/null +++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c @@ -0,0 +1,200 @@ +/* + * + * Copyright (C) 2010 Eric Bénard <eric@eukrea.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <linux/i2c.h> +#include <linux/gpio.h> +#include <linux/io.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/fsl_devices.h> +#include <linux/i2c/tsc2007.h> +#include <linux/leds.h> +#include <linux/input/matrix_keypad.h> + +#include <mach/common.h> +#include <mach/hardware.h> +#include <mach/imx-uart.h> +#include <mach/iomux-mx51.h> + +#include <asm/mach/arch.h> + +#include "devices.h" + +#define MBIMX51_TSC2007_GPIO (2*32 + 30) +#define MBIMX51_TSC2007_IRQ (MXC_INTERNAL_IRQS + MBIMX51_TSC2007_GPIO) +#define MBIMX51_LED0 (2*32 + 5) +#define MBIMX51_LED1 (2*32 + 6) +#define MBIMX51_LED2 (2*32 + 7) +#define MBIMX51_LED3 (2*32 + 8) + +static struct gpio_led mbimx51_leds[] = { + { + .name = "led0", + .default_trigger = "heartbeat", + .active_low = 1, + .gpio = MBIMX51_LED0, + }, + { + .name = "led1", + .default_trigger = "nand-disk", + .active_low = 1, + .gpio = MBIMX51_LED1, + }, + { + .name = "led2", + .default_trigger = "mmc0", + .active_low = 1, + .gpio = MBIMX51_LED2, + }, + { + .name = "led3", + .default_trigger = "default-on", + .active_low = 1, + .gpio = MBIMX51_LED3, + }, +}; + +static struct gpio_led_platform_data mbimx51_leds_info = { + .leds = mbimx51_leds, + .num_leds = ARRAY_SIZE(mbimx51_leds), +}; + +static struct platform_device mbimx51_leds_gpio = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &mbimx51_leds_info, + }, +}; + +static struct platform_device *devices[] __initdata = { + &mbimx51_leds_gpio, +}; + +static struct pad_desc mbimx51_pads[] = { + /* UART2 */ + MX51_PAD_UART2_RXD__UART2_RXD, + MX51_PAD_UART2_TXD__UART2_TXD, + + /* UART3 */ + MX51_PAD_UART3_RXD__UART3_RXD, + MX51_PAD_UART3_TXD__UART3_TXD, + MX51_PAD_KEY_COL4__UART3_RTS, + MX51_PAD_KEY_COL5__UART3_CTS, + + /* TSC2007 IRQ */ + MX51_PAD_NANDF_D10__GPIO_3_30, + + /* LEDS */ + MX51_PAD_DISPB2_SER_DIN__GPIO_3_5, + MX51_PAD_DISPB2_SER_DIO__GPIO_3_6, + MX51_PAD_DISPB2_SER_CLK__GPIO_3_7, + MX51_PAD_DISPB2_SER_RS__GPIO_3_8, + + /* KPP */ + MX51_PAD_KEY_ROW0__KEY_ROW0, + MX51_PAD_KEY_ROW1__KEY_ROW1, + MX51_PAD_KEY_ROW2__KEY_ROW2, + MX51_PAD_KEY_ROW3__KEY_ROW3, + MX51_PAD_KEY_COL0__KEY_COL0, + MX51_PAD_KEY_COL1__KEY_COL1, + MX51_PAD_KEY_COL2__KEY_COL2, + MX51_PAD_KEY_COL3__KEY_COL3, +}; + +static struct imxuart_platform_data uart_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static int mbimx51_keymap[] = { + KEY(0, 0, KEY_1), + KEY(0, 1, KEY_2), + KEY(0, 2, KEY_3), + KEY(0, 3, KEY_UP), + + KEY(1, 0, KEY_4), + KEY(1, 1, KEY_5), + KEY(1, 2, KEY_6), + KEY(1, 3, KEY_LEFT), + + KEY(2, 0, KEY_7), + KEY(2, 1, KEY_8), + KEY(2, 2, KEY_9), + KEY(2, 3, KEY_RIGHT), + + KEY(3, 0, KEY_0), + KEY(3, 1, KEY_DOWN), + KEY(3, 2, KEY_ESC), + KEY(3, 3, KEY_ENTER), +}; + +static struct matrix_keymap_data mbimx51_map_data = { + .keymap = mbimx51_keymap, + .keymap_size = ARRAY_SIZE(mbimx51_keymap), +}; + +static int tsc2007_get_pendown_state(void) +{ + return !gpio_get_value(MBIMX51_TSC2007_GPIO); +} + +struct tsc2007_platform_data tsc2007_data = { + .model = 2007, + .x_plate_ohms = 180, + .get_pendown_state = tsc2007_get_pendown_state, +}; + +static struct i2c_board_info mbimx51_i2c_devices[] = { + { + I2C_BOARD_INFO("tsc2007", 0x48), + .irq = MBIMX51_TSC2007_IRQ, + .platform_data = &tsc2007_data, + }, +}; + +/* + * baseboard initialization. + */ +void __init eukrea_mbimx51_baseboard_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mbimx51_pads, + ARRAY_SIZE(mbimx51_pads)); + + mxc_register_device(&mxc_uart_device1, NULL); + mxc_register_device(&mxc_uart_device2, &uart_pdata); + + gpio_request(MBIMX51_LED0, "LED0"); + gpio_direction_output(MBIMX51_LED0, 1); + gpio_free(MBIMX51_LED0); + gpio_request(MBIMX51_LED1, "LED1"); + gpio_direction_output(MBIMX51_LED1, 1); + gpio_free(MBIMX51_LED1); + gpio_request(MBIMX51_LED2, "LED2"); + gpio_direction_output(MBIMX51_LED2, 1); + gpio_free(MBIMX51_LED2); + gpio_request(MBIMX51_LED3, "LED3"); + gpio_direction_output(MBIMX51_LED3, 1); + gpio_free(MBIMX51_LED3); + + platform_add_devices(devices, ARRAY_SIZE(devices)); + + mxc_register_device(&mxc_keypad_device, &mbimx51_map_data); + + gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq"); + gpio_direction_input(MBIMX51_TSC2007_GPIO); + set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING); + i2c_register_board_info(1, mbimx51_i2c_devices, + ARRAY_SIZE(mbimx51_i2c_devices)); +} diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index b7677ef80cc..bc3f30db8d9 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c @@ -65,6 +65,8 @@ void __init mx51_map_io(void) iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); } +int imx51_register_gpios(void); + void __init mx51_init_irq(void) { unsigned long tzic_addr; @@ -80,4 +82,5 @@ void __init mx51_init_irq(void) panic("unable to map TZIC interrupt controller\n"); tzic_init_irq(tzic_virt); + imx51_register_gpios(); } diff --git a/arch/arm/mach-mxc91231/crm_regs.h b/arch/arm/mach-mxc91231/crm_regs.h index ce4f5905818..b989baccd67 100644 --- a/arch/arm/mach-mxc91231/crm_regs.h +++ b/arch/arm/mach-mxc91231/crm_regs.h @@ -11,11 +11,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * */ #ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ diff --git a/arch/arm/mach-mxc91231/devices.c b/arch/arm/mach-mxc91231/devices.c index 353bd977b39..027af4f0d18 100644 --- a/arch/arm/mach-mxc91231/devices.c +++ b/arch/arm/mach-mxc91231/devices.c @@ -135,7 +135,7 @@ static struct mxc_gpio_port mxc_gpio_ports[] = { }, }; -int __init mxc_register_gpios(void) +int __init mxc91231_register_gpios(void) { return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); } diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c index 6becda3ff33..aeccfd755fe 100644 --- a/arch/arm/mach-mxc91231/mm.c +++ b/arch/arm/mach-mxc91231/mm.c @@ -15,11 +15,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * */ #include <linux/mm.h> @@ -88,7 +83,10 @@ void __init mxc91231_map_io(void) iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); } +int mxc91231_register_gpios(void); + void __init mxc91231_init_irq(void) { + mxc91231_register_gpios(); mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR)); } diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c new file mode 100644 index 00000000000..639c54a0799 --- /dev/null +++ b/arch/arm/plat-mxc/3ds_debugboard.c @@ -0,0 +1,202 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/smsc911x.h> + +#include <mach/hardware.h> + +/* LAN9217 ethernet base address */ +#define LAN9217_BASE_ADDR(n) (n + 0x0) +/* External UART */ +#define UARTA_BASE_ADDR(n) (n + 0x8000) +#define UARTB_BASE_ADDR(n) (n + 0x10000) + +#define BOARD_IO_ADDR(n) (n + 0x20000) +/* LED switchs */ +#define LED_SWITCH_REG 0x00 +/* buttons */ +#define SWITCH_BUTTONS_REG 0x08 +/* status, interrupt */ +#define INTR_STATUS_REG 0x10 +#define INTR_MASK_REG 0x38 +#define INTR_RESET_REG 0x20 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER1_REG 0x40 +#define MAGIC_NUMBER2_REG 0x48 +/* CPLD code version */ +#define CPLD_CODE_VER_REG 0x50 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER3_REG 0x58 +/* module reset register*/ +#define MODULE_RESET_REG 0x60 +/* CPU ID and Personality ID */ +#define MCU_BOARD_ID_REG 0x68 + +#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_BOARD_IRQ_START) +#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_INTERNAL_IRQS) + +#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) +#define MXC_MAX_EXP_IO_LINES 16 + +/* interrupts like external uart , external ethernet etc*/ +#define EXPIO_INT_ENET (MXC_BOARD_IRQ_START + 0) +#define EXPIO_INT_XUART_A (MXC_BOARD_IRQ_START + 1) +#define EXPIO_INT_XUART_B (MXC_BOARD_IRQ_START + 2) +#define EXPIO_INT_BUTTON_A (MXC_BOARD_IRQ_START + 3) +#define EXPIO_INT_BUTTON_B (MXC_BOARD_IRQ_START + 4) + +static void __iomem *brd_io; +static void expio_ack_irq(u32 irq); + +static struct resource smsc911x_resources[] = { + { + .flags = IORESOURCE_MEM, + } , { + .start = EXPIO_INT_ENET, + .end = EXPIO_INT_ENET, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc911x_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY, +}; + +static struct platform_device smsc_lan9217_device = { + .name = "smsc911x", + .id = 0, + .dev = { + .platform_data = &smsc911x_config, + }, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, +}; + +static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) +{ + u32 imr_val; + u32 int_valid; + u32 expio_irq; + + desc->chip->mask(irq); /* irq = gpio irq number */ + + imr_val = __raw_readw(brd_io + INTR_MASK_REG); + int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val; + + expio_irq = MXC_BOARD_IRQ_START; + for (; int_valid != 0; int_valid >>= 1, expio_irq++) { + struct irq_desc *d; + if ((int_valid & 1) == 0) + continue; + d = irq_desc + expio_irq; + if (unlikely(!(d->handle_irq))) + pr_err("\nEXPIO irq: %d unhandled\n", expio_irq); + else + d->handle_irq(expio_irq, d); + } + + desc->chip->ack(irq); + desc->chip->unmask(irq); +} + +/* + * Disable an expio pin's interrupt by setting the bit in the imr. + * Irq is an expio virtual irq number + */ +static void expio_mask_irq(u32 irq) +{ + u16 reg; + u32 expio = MXC_IRQ_TO_EXPIO(irq); + + reg = __raw_readw(brd_io + INTR_MASK_REG); + reg |= (1 << expio); + __raw_writew(reg, brd_io + INTR_MASK_REG); +} + +static void expio_ack_irq(u32 irq) +{ + u32 expio = MXC_IRQ_TO_EXPIO(irq); + + __raw_writew(1 << expio, brd_io + INTR_RESET_REG); + __raw_writew(0, brd_io + INTR_RESET_REG); + expio_mask_irq(irq); +} + +static void expio_unmask_irq(u32 irq) +{ + u16 reg; + u32 expio = MXC_IRQ_TO_EXPIO(irq); + + reg = __raw_readw(brd_io + INTR_MASK_REG); + reg &= ~(1 << expio); + __raw_writew(reg, brd_io + INTR_MASK_REG); +} + +static struct irq_chip expio_irq_chip = { + .ack = expio_ack_irq, + .mask = expio_mask_irq, + .unmask = expio_unmask_irq, +}; + +int __init mxc_expio_init(u32 base, u32 p_irq) +{ + int i; + + brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K); + if (brd_io == NULL) + return -ENOMEM; + + if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) || + (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) || + (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) { + pr_info("3-Stack Debug board not detected\n"); + iounmap(brd_io); + brd_io = NULL; + return -ENODEV; + } + + pr_info("3-Stack Debug board detected, rev = 0x%04X\n", + readw(brd_io + CPLD_CODE_VER_REG)); + + /* + * Configure INT line as GPIO input + */ + gpio_request(MXC_IRQ_TO_GPIO(p_irq), "expio_pirq"); + gpio_direction_input(MXC_IRQ_TO_GPIO(p_irq)); + + /* disable the interrupt and clear the status */ + __raw_writew(0, brd_io + INTR_MASK_REG); + __raw_writew(0xFFFF, brd_io + INTR_RESET_REG); + __raw_writew(0, brd_io + INTR_RESET_REG); + __raw_writew(0x1F, brd_io + INTR_MASK_REG); + for (i = MXC_EXP_IO_BASE; + i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) { + set_irq_chip(i, &expio_irq_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + set_irq_type(p_irq, IRQF_TRIGGER_LOW); + set_irq_chained_handler(p_irq, mxc_expio_irq_handler); + + /* Register Lan device on the debugboard */ + smsc911x_resources[0].start = LAN9217_BASE_ADDR(base); + smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1; + platform_device_register(&smsc_lan9217_device); + + return 0; +} diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 7f7ad6f289b..0527e65318f 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -1,5 +1,7 @@ if ARCH_MXC +source "arch/arm/plat-mxc/devices/Kconfig" + menu "Freescale MXC Implementations" choice @@ -8,15 +10,12 @@ choice config ARCH_MX1 bool "MX1-based" - select CPU_ARM920T - select IMX_HAVE_IOMUX_V1 + select SOC_IMX1 help This enables support for systems based on the Freescale i.MX1 family config ARCH_MX2 bool "MX2-based" - select CPU_ARM926T - select IMX_HAVE_IOMUX_V1 help This enables support for systems based on the Freescale i.MX2 family @@ -25,6 +24,7 @@ config ARCH_MX25 select CPU_ARM926T select ARCH_MXC_IOMUX_V3 select HAVE_FB_IMX + select ARCH_MXC_AUDMUX_V2 help This enables support for systems based on the Freescale i.MX25 family @@ -48,8 +48,7 @@ config ARCH_MX5 endchoice -source "arch/arm/mach-mx1/Kconfig" -source "arch/arm/mach-mx2/Kconfig" +source "arch/arm/mach-imx/Kconfig" source "arch/arm/mach-mx3/Kconfig" source "arch/arm/mach-mx25/Kconfig" source "arch/arm/mach-mxc91231/Kconfig" @@ -81,6 +80,17 @@ config MXC_PWM help Enable support for the i.MX PWM controller(s). +config MXC_DEBUG_BOARD + bool "Enable MXC debug board(for 3-stack)" + help + The debug board is an integral part of the MXC 3-stack(PDK) + platforms, it can be attached or removed from the peripheral + board. On debug board, several debug devices(ethernet, UART, + buttons, LEDs and JTAG) are implemented. Between the MCU and + these devices, a CPLD is added as a bridge which performs + data/address de-multiplexing and decode, signal level shift, + interrupt control and various board functions. + config MXC_ULPI bool diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 895bc3c5e0c..78d405ed861 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -8,8 +8,6 @@ obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o # MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o) obj-$(CONFIG_MXC_TZIC) += tzic.o -obj-$(CONFIG_ARCH_MX1) += dma-mx1-mx2.o -obj-$(CONFIG_ARCH_MX2) += dma-mx1-mx2.o obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o obj-$(CONFIG_MXC_PWM) += pwm.o @@ -17,7 +15,10 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci.o obj-$(CONFIG_MXC_ULPI) += ulpi.o obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o +obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o ifdef CONFIG_SND_IMX_SOC obj-y += ssi-fiq.o obj-y += ssi-fiq-ksym.o endif + +obj-y += devices/ diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c index b62917ca3f9..1180bef7664 100644 --- a/arch/arm/plat-mxc/audmux-v1.c +++ b/arch/arm/plat-mxc/audmux-v1.c @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include <linux/module.h> diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c index 0c2cc5cd4d8..f9e7cdbd000 100644 --- a/arch/arm/plat-mxc/audmux-v2.c +++ b/arch/arm/plat-mxc/audmux-v2.c @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include <linux/module.h> @@ -191,6 +187,7 @@ static int mxc_audmux_v2_init(void) { int ret; +#if defined(CONFIG_ARCH_MX3) if (cpu_is_mx31()) audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR); @@ -204,7 +201,19 @@ static int mxc_audmux_v2_init(void) } audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR); } - +#endif +#if defined(CONFIG_ARCH_MX25) + if (cpu_is_mx25()) { + audmux_clk = clk_get(NULL, "audmux"); + if (IS_ERR(audmux_clk)) { + ret = PTR_ERR(audmux_clk); + printk(KERN_ERR "%s: cannot get clock: %d\n", __func__, + ret); + return ret; + } + audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR); + } +#endif audmux_debugfs_init(); return 0; diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c index 323ff8ccc87..2ed3ab173ad 100644 --- a/arch/arm/plat-mxc/clock.c +++ b/arch/arm/plat-mxc/clock.c @@ -52,13 +52,14 @@ static void __clk_disable(struct clk *clk) { if (clk == NULL || IS_ERR(clk)) return; - - __clk_disable(clk->parent); - __clk_disable(clk->secondary); - WARN_ON(!clk->usecount); - if (!(--clk->usecount) && clk->disable) - clk->disable(clk); + + if (!(--clk->usecount)) { + if (clk->disable) + clk->disable(clk); + __clk_disable(clk->parent); + __clk_disable(clk->secondary); + } } static int __clk_enable(struct clk *clk) @@ -66,12 +67,13 @@ static int __clk_enable(struct clk *clk) if (clk == NULL || IS_ERR(clk)) return -EINVAL; - __clk_enable(clk->parent); - __clk_enable(clk->secondary); - - if (clk->usecount++ == 0 && clk->enable) - clk->enable(clk); + if (clk->usecount++ == 0) { + __clk_enable(clk->parent); + __clk_enable(clk->secondary); + if (clk->enable) + clk->enable(clk); + } return 0; } @@ -160,17 +162,28 @@ EXPORT_SYMBOL(clk_set_rate); int clk_set_parent(struct clk *clk, struct clk *parent) { int ret = -EINVAL; + struct clk *old; if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent) || clk->set_parent == NULL) return ret; + if (clk->usecount) + clk_enable(parent); + mutex_lock(&clocks_mutex); ret = clk->set_parent(clk, parent); - if (ret == 0) + if (ret == 0) { + old = clk->parent; clk->parent = parent; + } else { + old = parent; + } mutex_unlock(&clocks_mutex); + if (clk->usecount) + clk_disable(old); + return ret; } EXPORT_SYMBOL(clk_set_parent); diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c index 56f2fb5cc45..735776d8495 100644 --- a/arch/arm/plat-mxc/devices.c +++ b/arch/arm/plat-mxc/devices.c @@ -18,6 +18,7 @@ #include <linux/kernel.h> #include <linux/init.h> +#include <linux/err.h> #include <linux/platform_device.h> #include <mach/common.h> @@ -35,3 +36,35 @@ int __init mxc_register_device(struct platform_device *pdev, void *data) return ret; } +struct platform_device *__init imx_add_platform_device(const char *name, int id, + const struct resource *res, unsigned int num_resources, + const void *data, size_t size_data) +{ + int ret = -ENOMEM; + struct platform_device *pdev; + + pdev = platform_device_alloc(name, id); + if (!pdev) + goto err; + + if (res) { + ret = platform_device_add_resources(pdev, res, num_resources); + if (ret) + goto err; + } + + if (data) { + ret = platform_device_add_data(pdev, data, size_data); + if (ret) + goto err; + } + + ret = platform_device_add(pdev); + if (ret) { +err: + platform_device_put(pdev); + return ERR_PTR(ret); + } + + return pdev; +} diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig new file mode 100644 index 00000000000..9ab784b776f --- /dev/null +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -0,0 +1,15 @@ +config IMX_HAVE_PLATFORM_FLEXCAN + select HAVE_CAN_FLEXCAN + bool + +config IMX_HAVE_PLATFORM_IMX_I2C + bool + +config IMX_HAVE_PLATFORM_IMX_UART + bool + +config IMX_HAVE_PLATFORM_MXC_NAND + bool + +config IMX_HAVE_PLATFORM_SPI_IMX + bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile new file mode 100644 index 00000000000..347da5161f7 --- /dev/null +++ b/arch/arm/plat-mxc/devices/Makefile @@ -0,0 +1,8 @@ +ifdef CONFIG_CAN_FLEXCAN +# the ifdef can be removed once the flexcan driver has been merged +obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o +endif +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o diff --git a/arch/arm/plat-mxc/devices/platform-flexcan.c b/arch/arm/plat-mxc/devices/platform-flexcan.c new file mode 100644 index 00000000000..5e97a01f14f --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-flexcan.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2010 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ + +#include <mach/devices-common.h> + +struct platform_device *__init imx_add_flexcan(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irq, + const struct flexcan_platform_data *pdata) +{ + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("flexcan", id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c new file mode 100644 index 00000000000..d0af9f7d8ae --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/devices-common.h> + +struct platform_device *__init imx_add_imx_i2c(int id, + resource_size_t iobase, resource_size_t iosize, int irq, + const struct imxi2c_platform_data *pdata) +{ + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-i2c", id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c new file mode 100644 index 00000000000..fa3dff1433e --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/devices-common.h> + +struct platform_device *__init imx_add_imx_uart_3irq(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irqrx, resource_size_t irqtx, + resource_size_t irqrts, + const struct imxuart_platform_data *pdata) +{ + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irqrx, + .end = irqrx, + .flags = IORESOURCE_IRQ, + }, { + .start = irqtx, + .end = irqtx, + .flags = IORESOURCE_IRQ, + }, { + .start = irqrts, + .end = irqrx, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} + +struct platform_device *__init imx_add_imx_uart_1irq(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irq, + const struct imxuart_platform_data *pdata) +{ + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c new file mode 100644 index 00000000000..1c286418d12 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <asm/sizes.h> +#include <mach/devices-common.h> + +static struct platform_device *__init imx_add_mxc_nand(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata, + resource_size_t iosize) +{ + static int id = 0; + + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("mxc_nand", id++, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} + +struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata) +{ + return imx_add_mxc_nand(iobase, irq, pdata, SZ_4K); +} + +struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata) +{ + return imx_add_mxc_nand(iobase, irq, pdata, SZ_8K); +} diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c new file mode 100644 index 00000000000..2831a6d3eb4 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <asm/sizes.h> +#include <mach/devices-common.h> + +struct platform_device *__init imx_add_spi_imx(int id, + resource_size_t iobase, resource_size_t iosize, int irq, + const struct spi_imx_master *pdata) +{ + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("spi_imx", id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 2a8646173c2..35a064ff02b 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -11,10 +11,6 @@ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software Foundation, - * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include <linux/platform_device.h> @@ -73,7 +69,51 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) { unsigned int v; -#ifdef CONFIG_ARCH_MX3 +#if defined(CONFIG_ARCH_MX25) + if (cpu_is_mx25()) { + v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + + USBCTRL_OTGBASE_OFFSET)); + + switch (port) { + case 0: /* OTG port */ + v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) + << MX35_OTG_SIC_SHIFT; + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX35_OTG_PM_BIT; + + break; + case 1: /* H1 port */ + v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | + MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) + << MX35_H1_SIC_SHIFT; + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX35_H1_PM_BIT; + + if (!(flags & MXC_EHCI_TTL_ENABLED)) + v |= MX35_H1_TLL_BIT; + + if (flags & MXC_EHCI_INTERNAL_PHY) + v |= MX35_H1_USBTE_BIT; + + if (flags & MXC_EHCI_IPPUE_DOWN) + v |= MX35_H1_IPPUE_DOWN_BIT; + + if (flags & MXC_EHCI_IPPUE_UP) + v |= MX35_H1_IPPUE_UP_BIT; + + break; + default: + return -EINVAL; + } + + writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + + USBCTRL_OTGBASE_OFFSET)); + return 0; + } +#endif /* CONFIG_ARCH_MX25 */ +#if defined(CONFIG_ARCH_MX3) if (cpu_is_mx31()) { v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 71437c61cfd..57ec4a896a5 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -214,13 +214,16 @@ static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset, struct mxc_gpio_port *port = container_of(chip, struct mxc_gpio_port, chip); u32 l; + unsigned long flags; + spin_lock_irqsave(&port->lock, flags); l = __raw_readl(port->base + GPIO_GDIR); if (dir) l |= 1 << offset; else l &= ~(1 << offset); __raw_writel(l, port->base + GPIO_GDIR); + spin_unlock_irqrestore(&port->lock, flags); } static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value) @@ -229,9 +232,12 @@ static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value) container_of(chip, struct mxc_gpio_port, chip); void __iomem *reg = port->base + GPIO_DR; u32 l; + unsigned long flags; + spin_lock_irqsave(&port->lock, flags); l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset); __raw_writel(l, reg); + spin_unlock_irqrestore(&port->lock, flags); } static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset) @@ -285,6 +291,8 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) port[i].chip.base = i * 32; port[i].chip.ngpio = 32; + spin_lock_init(&port[i].lock); + /* its a serious configuration bug when it fails */ BUG_ON( gpiochip_add(&port[i].chip) < 0 ); @@ -292,6 +300,12 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) /* setup one handler for each entry */ set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); set_irq_data(port[i].irq, &port[i]); + if (port[i].irq_high) { + /* setup handler for GPIO 16 to 31 */ + set_irq_chained_handler(port[i].irq_high, + mx3_gpio_irq_handler); + set_irq_data(port[i].irq_high, &port[i]); + } } } diff --git a/arch/arm/plat-mxc/include/mach/3ds_debugboard.h b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h new file mode 100644 index 00000000000..a384fdd49c6 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h @@ -0,0 +1,18 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_3DS_DB_H__ +#define __ASM_ARCH_MXC_3DS_DB_H__ + +extern int __init mxc_expio_init(u32 base, u32 p_irq); + +#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h deleted file mode 100644 index 0376c133c9f..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>. - * All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__ -#define __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__ - -#endif diff --git a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h deleted file mode 100644 index 93cc66f104c..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ -#ifndef __ARM_ARCH_BOARD_KZM_ARM11_H -#define __ARM_ARCH_BOARD_KZM_ARM11_H - -/* - * KZM-ARM11-01 Board Control Registers on FPGA - */ -#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000) -#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001) -#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002) -#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004) -#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008) -#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010) -#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020) -#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003) - -/* - * External UART for touch panel on FPGA - */ -#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050) - -#endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */ - diff --git a/arch/arm/plat-mxc/include/mach/board-mx21ads.h b/arch/arm/plat-mxc/include/mach/board-mx21ads.h deleted file mode 100644 index 0cf4fa29510..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx21ads.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX21ADS_H__ -#define __ASM_ARCH_MXC_BOARD_MX21ADS_H__ - -/* - * Memory-mapped I/O on MX21ADS base board - */ -#define MX21ADS_MMIO_BASE_ADDR 0xF5000000 -#define MX21ADS_MMIO_SIZE SZ_16M - -#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \ - (MX21ADS_MMIO_BASE_ADDR + (offset)) - -#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11) -#define MX21ADS_CS8900A_IOBASE_REG MX21ADS_REG_ADDR(0x000000) -#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000) -#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000) -#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000) - -/* MX21ADS_IO_REG bit definitions */ -#define MX21ADS_IO_SD_WP 0x0001 /* read */ -#define MX21ADS_IO_TP6 0x0001 /* write */ -#define MX21ADS_IO_SW_SEL 0x0002 /* read */ -#define MX21ADS_IO_TP7 0x0002 /* write */ -#define MX21ADS_IO_RESET_E_UART 0x0004 -#define MX21ADS_IO_RESET_BASE 0x0008 -#define MX21ADS_IO_CSI_CTL2 0x0010 -#define MX21ADS_IO_CSI_CTL1 0x0020 -#define MX21ADS_IO_CSI_CTL0 0x0040 -#define MX21ADS_IO_UART1_EN 0x0080 -#define MX21ADS_IO_UART4_EN 0x0100 -#define MX21ADS_IO_LCDON 0x0200 -#define MX21ADS_IO_IRDA_EN 0x0400 -#define MX21ADS_IO_IRDA_FIR_SEL 0x0800 -#define MX21ADS_IO_IRDA_MD0_B 0x1000 -#define MX21ADS_IO_IRDA_MD1 0x2000 -#define MX21ADS_IO_LED4_ON 0x4000 -#define MX21ADS_IO_LED3_ON 0x8000 - -#endif /* __ASM_ARCH_MXC_BOARD_MX21ADS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h deleted file mode 100644 index 7776d230327..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h +++ /dev/null @@ -1,344 +0,0 @@ -/* - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__ -#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__ - -/* external interrupt multiplexer */ -#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) - -#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES) -#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE -#define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1) -#define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2) - -#define MXC_MAX_BOARD_INTS (MXC_MAX_EXP_IO_LINES + \ - MXC_MAX_VIRTUAL_INTS) - -/* - * @name Memory Size parameters - */ - -/* - * Size of SDRAM memory - */ -#define SDRAM_MEM_SIZE SZ_128M - -/* - * PBC Controller parameters - */ - -/* - * Base address of PBC controller, CS4 - */ -#define PBC_BASE_ADDRESS 0xf4300000 -#define PBC_REG_ADDR(offset) (void __force __iomem *) \ - (PBC_BASE_ADDRESS + (offset)) - -/* - * PBC Interupt name definitions - */ -#define PBC_GPIO1_0 0 -#define PBC_GPIO1_1 1 -#define PBC_GPIO1_2 2 -#define PBC_GPIO1_3 3 -#define PBC_GPIO1_4 4 -#define PBC_GPIO1_5 5 - -#define PBC_INTR_MAX_NUM 6 -#define PBC_INTR_SHARED_MAX_NUM 8 - -/* When the PBC address connection is fixed in h/w, defined as 1 */ -#define PBC_ADDR_SH 0 - -/* Offsets for the PBC Controller register */ -/* - * PBC Board version register offset - */ -#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH) -/* - * PBC Board control register 1 set address. - */ -#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH) -/* - * PBC Board control register 1 clear address. - */ -#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH) -/* - * PBC Board control register 2 set address. - */ -#define PBC_BCTRL2_SET_REG PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH) -/* - * PBC Board control register 2 clear address. - */ -#define PBC_BCTRL2_CLEAR_REG PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH) -/* - * PBC Board control register 3 set address. - */ -#define PBC_BCTRL3_SET_REG PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH) -/* - * PBC Board control register 3 clear address. - */ -#define PBC_BCTRL3_CLEAR_REG PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH) -/* - * PBC Board control register 3 set address. - */ -#define PBC_BCTRL4_SET_REG PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH) -/* - * PBC Board control register 4 clear address. - */ -#define PBC_BCTRL4_CLEAR_REG PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH) -/*PBC_ADDR_SH - * PBC Board status register 1. - */ -#define PBC_BSTAT1_REG PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH) -/* - * PBC Board interrupt status register. - */ -#define PBC_INTSTATUS_REG PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH) -/* - * PBC Board interrupt current status register. - */ -#define PBC_INTCURR_STATUS_REG PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH) -/* - * PBC Interrupt mask register set address. - */ -#define PBC_INTMASK_SET_REG PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH) -/* - * PBC Interrupt mask register clear address. - */ -#define PBC_INTMASK_CLEAR_REG PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH) -/* - * External UART A. - */ -#define PBC_SC16C652_UARTA_REG PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH) -/* - * UART 4 Expanding Signal Status. - */ -#define PBC_UART_STATUS_REG PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH) -/* - * UART 4 Expanding Signal Control Set. - */ -#define PBC_UCTRL_SET_REG PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH) -/* - * UART 4 Expanding Signal Control Clear. - */ -#define PBC_UCTRL_CLR_REG PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH) -/* - * Ethernet Controller IO base address. - */ -#define PBC_CS8900A_IOBASE_REG PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH) -/* - * Ethernet Controller Memory base address. - */ -#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH) -/* - * Ethernet Controller DMA base address. - */ -#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH) - -/* PBC Board Version Register bit definition */ -#define PBC_VERSION_ADS 0x8000 /* Bit15=1 means version for ads */ -#define PBC_VERSION_EVB_REVB 0x4000 /* BIT14=1 means version for evb revb */ - -/* PBC Board Control Register 1 bit definitions */ -#define PBC_BCTRL1_ERST 0x0001 /* Ethernet Reset */ -#define PBC_BCTRL1_URST 0x0002 /* Reset External UART controller */ -#define PBC_BCTRL1_FRST 0x0004 /* FEC Reset */ -#define PBC_BCTRL1_ESLEEP 0x0010 /* Enable ethernet Sleep */ -#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */ - -/* PBC Board Control Register 2 bit definitions */ -#define PBC_BCTRL2_VCC_EN 0x0004 /* Enable VCC */ -#define PBC_BCTRL2_VPP_EN 0x0008 /* Enable Vpp */ -#define PBC_BCTRL2_ATAFEC_EN 0X0010 -#define PBC_BCTRL2_ATAFEC_SEL 0X0020 -#define PBC_BCTRL2_ATA_EN 0X0040 -#define PBC_BCTRL2_IRDA_SD 0X0080 -#define PBC_BCTRL2_IRDA_EN 0X0100 -#define PBC_BCTRL2_CCTL10 0X0200 -#define PBC_BCTRL2_CCTL11 0X0400 - -/* PBC Board Control Register 3 bit definitions */ -#define PBC_BCTRL3_HSH_EN 0X0020 -#define PBC_BCTRL3_FSH_MOD 0X0040 -#define PBC_BCTRL3_OTG_HS_EN 0X0080 -#define PBC_BCTRL3_OTG_VBUS_EN 0X0100 -#define PBC_BCTRL3_FSH_VBUS_EN 0X0200 -#define PBC_BCTRL3_USB_OTG_ON 0X0800 -#define PBC_BCTRL3_USB_FSH_ON 0X1000 - -/* PBC Board Control Register 4 bit definitions */ -#define PBC_BCTRL4_REGEN_SEL 0X0001 -#define PBC_BCTRL4_USER_OFF 0X0002 -#define PBC_BCTRL4_VIB_EN 0X0004 -#define PBC_BCTRL4_PWRGT1_EN 0X0008 -#define PBC_BCTRL4_PWRGT2_EN 0X0010 -#define PBC_BCTRL4_STDBY_PRI 0X0020 - -#ifndef __ASSEMBLY__ -/* - * Enumerations for SD cards and memory stick card. This corresponds to - * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN. - */ -enum mxc_card_no { - MXC_CARD_SD2 = 0, - MXC_CARD_SD3, - MXC_CARD_MS, - MXC_CARD_SD1, - MXC_CARD_MIN = MXC_CARD_SD2, - MXC_CARD_MAX = MXC_CARD_SD1, -}; -#endif - -#define MXC_CPLD_VER_1_50 0x01 - -/* - * PBC BSTAT Register bit definitions - */ -#define PBC_BSTAT_PRI_INT 0X0001 -#define PBC_BSTAT_USB_BYP 0X0002 -#define PBC_BSTAT_ATA_IOCS16 0X0004 -#define PBC_BSTAT_ATA_CBLID 0X0008 -#define PBC_BSTAT_ATA_DASP 0X0010 -#define PBC_BSTAT_PWR_RDY 0X0020 -#define PBC_BSTAT_SD3_WP 0X0100 -#define PBC_BSTAT_SD2_WP 0X0200 -#define PBC_BSTAT_SD1_WP 0X0400 -#define PBC_BSTAT_SD3_DET 0X0800 -#define PBC_BSTAT_SD2_DET 0X1000 -#define PBC_BSTAT_SD1_DET 0X2000 -#define PBC_BSTAT_MS_DET 0X4000 -#define PBC_BSTAT_SD3_DET_BIT 11 -#define PBC_BSTAT_SD2_DET_BIT 12 -#define PBC_BSTAT_SD1_DET_BIT 13 -#define PBC_BSTAT_MS_DET_BIT 14 -#define MXC_BSTAT_BIT(n) ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \ - ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \ - ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \ - ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \ - 0x0)))) - -/* - * PBC UART Control Register bit definitions - */ -#define PBC_UCTRL_DCE_DCD 0X0001 -#define PBC_UCTRL_DCE_DSR 0X0002 -#define PBC_UCTRL_DCE_RI 0X0004 -#define PBC_UCTRL_DTE_DTR 0X0100 - -/* - * PBC UART Status Register bit definitions - */ -#define PBC_USTAT_DTE_DCD 0X0001 -#define PBC_USTAT_DTE_DSR 0X0002 -#define PBC_USTAT_DTE_RI 0X0004 -#define PBC_USTAT_DCE_DTR 0X0100 - -/* - * PBC Interupt mask register bit definitions - */ -#define PBC_INTR_SD3_R_EN_BIT 4 -#define PBC_INTR_SD2_R_EN_BIT 0 -#define PBC_INTR_SD1_R_EN_BIT 6 -#define PBC_INTR_MS_R_EN_BIT 5 -#define PBC_INTR_SD3_EN_BIT 13 -#define PBC_INTR_SD2_EN_BIT 12 -#define PBC_INTR_MS_EN_BIT 14 -#define PBC_INTR_SD1_EN_BIT 15 - -#define PBC_INTR_SD2_R_EN 0x0001 -#define PBC_INTR_LOW_BAT 0X0002 -#define PBC_INTR_OTG_FSOVER 0X0004 -#define PBC_INTR_FSH_OVER 0X0008 -#define PBC_INTR_SD3_R_EN 0x0010 -#define PBC_INTR_MS_R_EN 0x0020 -#define PBC_INTR_SD1_R_EN 0x0040 -#define PBC_INTR_FEC_INT 0X0080 -#define PBC_INTR_ENET_INT 0X0100 -#define PBC_INTR_OTGFS_INT 0X0200 -#define PBC_INTR_XUART_INT 0X0400 -#define PBC_INTR_CCTL12 0X0800 -#define PBC_INTR_SD2_EN 0x1000 -#define PBC_INTR_SD3_EN 0x2000 -#define PBC_INTR_MS_EN 0x4000 -#define PBC_INTR_SD1_EN 0x8000 - - - -/* For interrupts like xuart, enet etc */ -#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX27_PIN_TIN) -#define MXC_MAX_EXP_IO_LINES 16 - -/* - * This corresponds to PBC_INTMASK_SET_REG at offset 0x38. - * - */ -#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 1) -#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2) -#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3) -#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4) -#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5) -#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6) -#define EXPIO_INT_FEC (MXC_EXP_IO_BASE + 7) -#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8) -#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9) -#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) -#define EXPIO_INT_CCTL12_INT (MXC_EXP_IO_BASE + 11) -#define EXPIO_INT_SD2_EN (MXC_EXP_IO_BASE + 12) -#define EXPIO_INT_SD3_EN (MXC_EXP_IO_BASE + 13) -#define EXPIO_INT_MS_EN (MXC_EXP_IO_BASE + 14) -#define EXPIO_INT_SD1_EN (MXC_EXP_IO_BASE + 15) - -/* - * This is System IRQ used by CS8900A for interrupt generation - * taken from platform.h - */ -#define CS8900AIRQ EXPIO_INT_ENET_INT -/* This is I/O Base address used to access registers of CS8900A on MXC ADS */ -#define CS8900A_BASE_ADDRESS (PBC_CS8900A_IOBASE_REG + 0x300) - -#define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX27_PIN_TOUT) - -/* -* This is used to detect if the CPLD version is for mx27 evb board rev-a -*/ -#define PBC_CPLD_VERSION_IS_REVA() \ - ((__raw_readw(PBC_VERSION_REG) & \ - (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\ - == 0) - -/* This is used to active or inactive ata signal in CPLD . - * It is dependent with hardware - */ -#define PBC_ATA_SIGNAL_ACTIVE() \ - __raw_writew( \ - PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \ - PBC_BCTRL2_CLEAR_REG) - -#define PBC_ATA_SIGNAL_INACTIVE() \ - __raw_writew( \ - PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \ - PBC_BCTRL2_SET_REG) - -#define MXC_BD_LED1 (1 << 5) -#define MXC_BD_LED2 (1 << 6) -#define MXC_BD_LED_ON(led) \ - __raw_writew(led, PBC_BCTRL1_SET_REG) -#define MXC_BD_LED_OFF(led) \ - __raw_writew(led, PBC_BCTRL1_CLEAR_REG) - -/* to determine the correct external crystal reference */ -#define CKIH_27MHZ_BIT_SET (1 << 3) - -#endif /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx27lite.h b/arch/arm/plat-mxc/include/mach/board-mx27lite.h deleted file mode 100644 index ea87551d273..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx27lite.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX27LITE_H__ -#define __ASM_ARCH_MXC_BOARD_MX27LITE_H__ - -#endif /* __ASM_ARCH_MXC_BOARD_MX27LITE_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h deleted file mode 100644 index fec1bcfa916..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX27PDK_H__ -#define __ASM_ARCH_MXC_BOARD_MX27PDK_H__ - -#endif /* __ASM_ARCH_MXC_BOARD_MX27PDK_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h deleted file mode 100644 index da92933a233..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ -#define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ - -/* Definitions for components on the Debug board */ - -/* Base address of CPLD controller on the Debug board */ -#define DEBUG_BASE_ADDRESS CS5_IO_ADDRESS(CS5_BASE_ADDR) - -/* LAN9217 ethernet base address */ -#define LAN9217_BASE_ADDR CS5_BASE_ADDR - -/* CPLD config and interrupt base address */ -#define CPLD_ADDR (DEBUG_BASE_ADDRESS + 0x20000) - -/* LED switchs */ -#define CPLD_LED_REG (CPLD_ADDR + 0x00) -/* buttons */ -#define CPLD_SWITCH_BUTTONS_REG (EXPIO_ADDR + 0x08) -/* status, interrupt */ -#define CPLD_INT_STATUS_REG (CPLD_ADDR + 0x10) -#define CPLD_INT_MASK_REG (CPLD_ADDR + 0x38) -#define CPLD_INT_RESET_REG (CPLD_ADDR + 0x20) -/* magic word for debug CPLD */ -#define CPLD_MAGIC_NUMBER1_REG (CPLD_ADDR + 0x40) -#define CPLD_MAGIC_NUMBER2_REG (CPLD_ADDR + 0x48) -/* CPLD code version */ -#define CPLD_CODE_VER_REG (CPLD_ADDR + 0x50) -/* magic word for debug CPLD */ -#define CPLD_MAGIC_NUMBER3_REG (CPLD_ADDR + 0x58) -/* module reset register */ -#define CPLD_MODULE_RESET_REG (CPLD_ADDR + 0x60) -/* CPU ID and Personality ID */ -#define CPLD_MCU_BOARD_ID_REG (CPLD_ADDR + 0x68) - -/* CPLD IRQ line for external uart, external ethernet etc */ -#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1) - -#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) -#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) - -#define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0) -#define EXPIO_INT_XUART_A (MXC_EXP_IO_BASE + 1) -#define EXPIO_INT_XUART_B (MXC_EXP_IO_BASE + 2) -#define EXPIO_INT_BUTTON_A (MXC_EXP_IO_BASE + 3) -#define EXPIO_INT_BUTTON_B (MXC_EXP_IO_BASE + 4) - -#define MXC_MAX_EXP_IO_LINES 16 - -#endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h deleted file mode 100644 index 095a199591c..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ -#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ - -#include <mach/hardware.h> - -/* Base address of PBC controller */ -#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT -/* Offsets for the PBC Controller register */ - -/* PBC Board status register offset */ -#define PBC_BSTAT 0x000002 - -/* PBC Board control register 1 set address */ -#define PBC_BCTRL1_SET 0x000004 - -/* PBC Board control register 1 clear address */ -#define PBC_BCTRL1_CLEAR 0x000006 - -/* PBC Board control register 2 set address */ -#define PBC_BCTRL2_SET 0x000008 - -/* PBC Board control register 2 clear address */ -#define PBC_BCTRL2_CLEAR 0x00000A - -/* PBC Board control register 3 set address */ -#define PBC_BCTRL3_SET 0x00000C - -/* PBC Board control register 3 clear address */ -#define PBC_BCTRL3_CLEAR 0x00000E - -/* PBC Board control register 4 set address */ -#define PBC_BCTRL4_SET 0x000010 - -/* PBC Board control register 4 clear address */ -#define PBC_BCTRL4_CLEAR 0x000012 - -/* PBC Board status register 1 */ -#define PBC_BSTAT1 0x000014 - -/* PBC Board interrupt status register */ -#define PBC_INTSTATUS 0x000016 - -/* PBC Board interrupt current status register */ -#define PBC_INTCURR_STATUS 0x000018 - -/* PBC Interrupt mask register set address */ -#define PBC_INTMASK_SET 0x00001A - -/* PBC Interrupt mask register clear address */ -#define PBC_INTMASK_CLEAR 0x00001C - -/* External UART A */ -#define PBC_SC16C652_UARTA 0x010000 - -/* External UART B */ -#define PBC_SC16C652_UARTB 0x010010 - -/* Ethernet Controller IO base address */ -#define PBC_CS8900A_IOBASE 0x020000 - -/* Ethernet Controller Memory base address */ -#define PBC_CS8900A_MEMBASE 0x021000 - -/* Ethernet Controller DMA base address */ -#define PBC_CS8900A_DMABASE 0x022000 - -/* External chip select 0 */ -#define PBC_XCS0 0x040000 - -/* LCD Display enable */ -#define PBC_LCD_EN_B 0x060000 - -/* Code test debug enable */ -#define PBC_CODE_B 0x070000 - -/* PSRAM memory select */ -#define PBC_PSRAM_B 0x5000000 - -#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) -#define PBC_INTCURR_STATUS_REG (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS) -#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS) -#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) -#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4) - -#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) -#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) - -#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0) -#define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1) -#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2) -#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3) -#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4) -#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5) -#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6) -#define EXPIO_INT_RES7 (MXC_EXP_IO_BASE + 7) -#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8) -#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9) -#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) -#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11) -#define EXPIO_INT_SYNTH_IRQ (MXC_EXP_IO_BASE + 12) -#define EXPIO_INT_CE_INT1 (MXC_EXP_IO_BASE + 13) -#define EXPIO_INT_CE_INT2 (MXC_EXP_IO_BASE + 14) -#define EXPIO_INT_RES15 (MXC_EXP_IO_BASE + 15) - -#define MXC_MAX_EXP_IO_LINES 16 - -#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h index eb5a5024622..0df71bfefbb 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h @@ -31,7 +31,7 @@ enum mx31lilly_boards { /* * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls baseboard's init function. + * its own devices, it calls the baseboard's init function. */ extern void mx31lilly_db_init(void); diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h index 2b2da036757..c1ad0ae807c 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h @@ -32,7 +32,7 @@ enum mx31lite_boards { /* * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls baseboard's init function. + * its own devices, it calls the baseboard's init function. */ extern void mx31lite_db_init(void); diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h index 36ff3cedee1..de14543891c 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h @@ -31,7 +31,7 @@ enum mx31moboard_boards { /* * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls baseboard's init function. + * its own devices, it calls the baseboard's init function. */ extern void mx31moboard_devboard_init(void); diff --git a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h b/arch/arm/plat-mxc/include/mach/board-mx35pdk.h deleted file mode 100644 index 383f1c04df0..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__ -#define __ASM_ARCH_MXC_BOARD_MX35PDK_H__ - -#endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-pcm037.h b/arch/arm/plat-mxc/include/mach/board-pcm037.h deleted file mode 100644 index 13411709b13..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-pcm037.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2008 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__ -#define __ASM_ARCH_MXC_BOARD_PCM037_H__ - -#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-pcm038.h b/arch/arm/plat-mxc/include/mach/board-pcm038.h index 410f9786ed2..6f371e35753 100644 --- a/arch/arm/plat-mxc/include/mach/board-pcm038.h +++ b/arch/arm/plat-mxc/include/mach/board-pcm038.h @@ -22,7 +22,7 @@ #ifndef __ASSEMBLY__ /* * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls baseboard's init function. + * its own devices, it calls the baseboard's init function. * TODO: Add your own baseboard init function and call it from * inside pcm038_init(). * diff --git a/arch/arm/plat-mxc/include/mach/board-pcm043.h b/arch/arm/plat-mxc/include/mach/board-pcm043.h deleted file mode 100644 index 1ac4e1682e5..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-pcm043.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2008 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__ -#define __ASM_ARCH_MXC_BOARD_PCM043_H__ - -#endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h deleted file mode 100644 index 6d88c7af4b2..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-qong.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com> - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_QONG_H__ -#define __ASM_ARCH_MXC_BOARD_QONG_H__ - -/* NOR FLASH */ -#define QONG_NOR_SIZE (128*1024*1024) - -#endif /* __ASM_ARCH_MXC_BOARD_QONG_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index 0b6e11eaeb8..25606409aab 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -23,8 +23,8 @@ #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif #include <mach/mx25.h> -#define UART_PADDR UART1_BASE_ADDR -#define UART_VADDR MX25_AIPS1_IO_ADDRESS(UART1_BASE_ADDR) +#define UART_PADDR MX25_UART1_BASE_ADDR +#define UART_VADDR MX25_AIPS1_IO_ADDRESS(MX25_UART1_BASE_ADDR) #endif #ifdef CONFIG_ARCH_MX2 diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h new file mode 100644 index 00000000000..c5f68c58730 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/init.h> + +struct platform_device *imx_add_platform_device(const char *name, int id, + const struct resource *res, unsigned int num_resources, + const void *data, size_t size_data); + +#if defined (CONFIG_CAN_FLEXCAN) || defined (CONFIG_CAN_FLEXCAN_MODULE) +#include <linux/can/platform/flexcan.h> +struct platform_device *__init imx_add_flexcan(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irq, + const struct flexcan_platform_data *pdata); +#else +/* the ifdef can be removed once the flexcan driver has been merged */ +struct flexcan_platform_data; +static inline struct platform_device *__init imx_add_flexcan(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irq, + const struct flexcan_platform_data *pdata) +{ + return NULL; +} +#endif + +#include <mach/i2c.h> +struct platform_device *__init imx_add_imx_i2c(int id, + resource_size_t iobase, resource_size_t iosize, int irq, + const struct imxi2c_platform_data *pdata); + +#include <mach/imx-uart.h> +struct platform_device *__init imx_add_imx_uart_3irq(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irqrx, resource_size_t irqtx, + resource_size_t irqrts, + const struct imxuart_platform_data *pdata); +struct platform_device *__init imx_add_imx_uart_1irq(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irq, + const struct imxuart_platform_data *pdata); + +#include <mach/mxc_nand.h> +struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata); +struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata); + +#include <mach/spi.h> +struct platform_device *__init imx_add_spi_imx(int id, + resource_size_t iobase, resource_size_t iosize, int irq, + const struct spi_imx_master *pdata); diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h index a1fd5830af4..634e3f4c454 100644 --- a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h +++ b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009 Eric Benard - eric@eukrea.com + * Copyright (C) 2010 Eric Benard - eric@eukrea.com * * Based on board-pcm038.h which is : * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) @@ -19,22 +19,29 @@ * MA 02110-1301, USA. */ -#ifndef __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ -#define __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ +#ifndef __MACH_EUKREA_BASEBOARDS_H__ +#define __MACH_EUKREA_BASEBOARDS_H__ #ifndef __ASSEMBLY__ /* * This CPU module needs a baseboard to work. After basic initializing * its own devices, it calls baseboard's init function. * TODO: Add your own baseboard init function and call it from - * inside eukrea_cpuimx27_init(). + * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init() + * eukrea_cpuimx35_init() or eukrea_cpuimx51_init(). * * This example here is for the development board. Refer - * eukrea_mbimx27-baseboard.c + * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25 + * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27 + * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35 + * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51 */ +extern void eukrea_mbimx25_baseboard_init(void); extern void eukrea_mbimx27_baseboard_init(void); +extern void eukrea_mbimx35_baseboard_init(void); +extern void eukrea_mbimx51_baseboard_init(void); #endif -#endif /* __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ */ +#endif /* __MACH_EUKREA_BASEBOARDS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h index 894d2f87c85..661fbc60575 100644 --- a/arch/arm/plat-mxc/include/mach/gpio.h +++ b/arch/arm/plat-mxc/include/mach/gpio.h @@ -33,9 +33,11 @@ struct mxc_gpio_port { void __iomem *base; int irq; + int irq_high; int virtual_irq_start; struct gpio_chip chip; u32 both_edges; + spinlock_t lock; }; int mxc_gpio_init(struct mxc_gpio_port*, int); diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h index f39220d1b67..d7f52c91f82 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h @@ -252,6 +252,7 @@ #define MX25_PAD_OE_ACD__GPIO_1_25 IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CONTRAST__CONTRAST IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CONTRAST__PWM4_PWMO IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CONTRAST__FEC_CRS IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL) #define MX25_PAD_PWM__PWM IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL) @@ -371,30 +372,41 @@ #define MX25_PAD_SD1_DATA3__FEC_CRS IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL) #define MX25_PAD_SD1_DATA3__GPIO_2_28 IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, PAD_CTL_PKE) +#define KPP_CTL_ROW (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define KPP_CTL_COL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) + +#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, KPP_CTL_ROW) #define MX25_PAD_KPP_ROW0__GPIO_2_29 IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW1__KPP_ROW1 IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, PAD_CTL_PKE) +#define MX25_PAD_KPP_ROW1__KPP_ROW1 IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, KPP_CTL_ROW) #define MX25_PAD_KPP_ROW1__GPIO_2_30 IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW2__KPP_ROW2 IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, PAD_CTL_PKE) +#define MX25_PAD_KPP_ROW2__KPP_ROW2 IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, KPP_CTL_ROW) #define MX25_PAD_KPP_ROW2__CSI_D0 IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL) #define MX25_PAD_KPP_ROW2__GPIO_2_31 IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW3__KPP_ROW3 IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, PAD_CTL_PKE) +#define MX25_PAD_KPP_ROW3__KPP_ROW3 IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, KPP_CTL_ROW) #define MX25_PAD_KPP_ROW3__CSI_LD1 IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL) #define MX25_PAD_KPP_ROW3__GPIO_3_0 IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL0__KPP_COL0 IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) +#define MX25_PAD_KPP_COL0__KPP_COL0 IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, KPP_CTL_COL) +#define MX25_PAD_KPP_COL0__UART4_RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL0__AUD5_TXD IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) #define MX25_PAD_KPP_COL0__GPIO_3_1 IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL1__KPP_COL1 IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) +#define MX25_PAD_KPP_COL1__KPP_COL1 IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, KPP_CTL_COL) +#define MX25_PAD_KPP_COL1__UART4_TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL1__AUD5_RXD IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) #define MX25_PAD_KPP_COL1__GPIO_3_2 IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL2__KPP_COL2 IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) +#define MX25_PAD_KPP_COL2__KPP_COL2 IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, KPP_CTL_COL) +#define MX25_PAD_KPP_COL2__UART4_RTS IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL2__AUD5_TXC IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) #define MX25_PAD_KPP_COL2__GPIO_3_3 IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) +#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, KPP_CTL_COL) +#define MX25_PAD_KPP_COL3__UART4_CTS IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL3__AUD5_TXFS IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) #define MX25_PAD_KPP_COL3__GPIO_3_4 IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL) #define MX25_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL) diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index ab0f95d953d..21bfa46785b 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -27,8 +27,8 @@ typedef enum iomux_config { IOMUX_CONFIG_ALT5, IOMUX_CONFIG_ALT6, IOMUX_CONFIG_ALT7, - IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ - IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ + IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ } iomux_pin_cfg_t; /* Pad control groupings */ @@ -38,6 +38,8 @@ typedef enum iomux_config { PAD_CTL_SRE_FAST) #define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ PAD_CTL_SRE_FAST) +#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) #define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_PKE | PAD_CTL_HYS) @@ -46,289 +48,278 @@ typedef enum iomux_config { /* * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named - * GPIO_<unit>_<num> see also iomux-v3.h + * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> + * See also iomux-v3.h */ -/* - * FIXME: This was converted using scripts from existing Freescale code to - * this form used upstream. Need to verify the name format. - */ - -/* PAD MUX ALT INPSE PATH PADCTRL */ - -#define MX51_PAD_GPIO_2_0__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_1__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_2__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) - -/* Babbage UART3 */ -#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL) -#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL) -#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL) -#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL) - -#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX51_PAD_GPIO_2_10__EIM_A16 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_11__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_12__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_13__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_14__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_15__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_16__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_17__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX51_PAD_GPIO_2_18__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_19__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_20__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_21__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_22__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_23__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX51_PAD_GPIO_2_24__EIM_OE IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_25__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_26__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_27__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_28__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_29__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_30__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_31__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX51_PAD_GPIO_3_1__EIM_LBA IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_2__EIM_CRE IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_3__NANDF_WE_B IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_4__NANDF_RE_B IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_5__NANDF_ALE IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_6__NANDF_CLE IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_7__NANDF_WP_B IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_8__NANDF_RB0 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_9__NANDF_RB1 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_10__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_11__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_12__GPIO_NAND IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) -/* REVISIT: Not sure of these values - - #define MX51_PAD_GPIO_1___NANDF_RB4 IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL) - #define MX51_PAD_GPIO_3_13__NANDF_RB5 IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL) - #define MX51_PAD_GPIO_3_15__NANDF_RB7 IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL) -*/ -#define MX51_PAD_GPIO_3_14__NANDF_RB6 IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_16__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_17__NANDF_CS1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_18__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_19__NANDF_CS3 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_20__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_21__NANDF_CS5 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_22__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_23__NANDF_CS7 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_25__NANDF_D15 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_26__NANDF_D14 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_27__NANDF_D13 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_28__NANDF_D12 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_29__NANDF_D11 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_30__NANDF_D10 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_31__NANDF_D9 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_0__NANDF_D8 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_1__NANDF_D7 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_2__NANDF_D6 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_3__NANDF_D5 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_5__NANDF_D3 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_6__NANDF_D2 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_7__NANDF_D1 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_8__NANDF_D0 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_12__CSI1_D8 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_13__CSI1_D9 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_9__CSI2_D12 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_10__CSI2_D13 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_11__CSI2_D14 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_12__CSI2_D15 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_11__CSI2_D16 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_12__CSI2_D17 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_11__CSI2_D18 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_12__CSI2_D19 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_13__CSI2_VSYNC IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_14__CSI2_HSYNC IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_PKE0__CSI2_PKE0 IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_16__I2C1_CLK IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_17__I2C1_DAT IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_20__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_21__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_22__CSPI1_MOSI IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_23__CSPI1_MISO IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_24__CSPI1_SS0 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_25__CSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_26__CSPI1_RDY IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_27__CSPI1_SCLK IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) - -/* Babbage UART1 */ -#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) -#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) -#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL) -#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL) - -/* Babbage UART2 */ -#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL) -#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL) - -#define MX51_PAD_GPIO_1_22__UART3_RXD IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_23__UART3_TXD IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_24__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_STP__GPIO_1_27 IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_GPIO_3_0__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_1__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_2__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_3__DI1_D0_CS IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_4__DI1_D1_CS IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_19__DISP2_DAT6 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_29__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_30__DISP2_DAT8 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_31__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_0__GPIO1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_1__GPIO1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_2__GPIO1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_3__GPIO1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \ - (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)) -#define MX51_PAD_GPIO_1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) - -/* EIM */ -#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL) +/* PAD MUX ALT INPSE PATH PADCTRL */ +#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D16__GPIO_2_0 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x05c, (4 | IOMUX_CONFIG_SION), \ + 0x09b4, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_EIM_D17__GPIO_2_1 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D18__GPIO_2_2 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D19__GPIO_2_3 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x068, (4 | IOMUX_CONFIG_SION), \ + 0x09b0, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_EIM_D20__GPIO_2_4 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D22__GPIO_2_6 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D23__GPIO_2_7 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, 3, 0x0, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, 0x0, 0, MX51_UART2_PAD_CTRL) +#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, 0x0, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART2_PAD_CTRL) +#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART3_PAD_CTRL) +#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A16__GPIO_2_10 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A17__GPIO_2_11 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A18__GPIO_2_12 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A19__GPIO_2_13 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A20__GPIO_2_14 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A21__GPIO_2_15 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A23__GPIO_2_17 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A24__GPIO_2_18 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A25__GPIO_2_19 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A26__GPIO_2_20 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A27__GPIO_2_21 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0x0FC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WE_B__GPIO_3_3 IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RE_B__GPIO_3_4 IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_ALE__GPIO_3_5 IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CLE__GPIO_3_6 IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WP_B__GPIO_3_7 IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D12__GPIO_3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D11__GPIO_3_29 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D10__GPIO_3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D9__GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D8__GPIO_4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D7__GPIO_4_1 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D6__GPIO_4_2 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D5__GPIO_4_3 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D4__GPIO_4_4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D3__GPIO_4_5 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D2__GPIO_4_6 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D1__GPIO_4_7 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D0__GPIO_4_8 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D8__GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D9__GPIO_3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x000, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x000, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x000, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D12__GPIO_4_9 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D13__GPIO_4_10 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D14__GPIO_4_11 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D15__GPIO_4_12 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D16__GPIO_4_11 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D17__GPIO_4_12 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D18__GPIO_4_11 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D19__GPIO_4_12 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_VSYNC__GPIO_4_13 IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_HSYNC__GPIO_4_14 IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15 IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_I2C1_CLK__GPIO_4_16 IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_I2C1_CLK__HSI2C_CLK IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_I2C1_DAT__GPIO_4_17 IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_I2C1_DAT__HSI2C_DAT IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) +#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) +#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL) +#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, 0x0, 0, MX51_UART1_PAD_CTRL) +#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL) +#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, 0, 0x0, 0, MX51_UART2_PAD_CTRL) +#define MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART3_PAD_CTRL) +#define MX51_PAD_UART3_RXD__GPIO_1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, 0x0, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_UART3_TXD__GPIO_1_23 IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_OWIRE_LINE__GPIO_1_24 IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65C, 0x26C, 2, 0x9f0, 4, MX51_UART3_PAD_CTRL) +#define MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65C, 0x26C, (3 | IOMUX_CONFIG_SION), \ + 0x09b8, 1, MX51_I2C_PAD_CTRL) +#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, 0, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, (3 | IOMUX_CONFIG_SION), \ + 0x09bc, 1, MX51_I2C_PAD_CTRL) +#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_STP__GPIO_1_27 IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_DI1_PIN11__GPIO_3_0 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT6__GPIO_1_19 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT7__GPIO_1_29 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT8__GPIO_1_30 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT9__GPIO_1_31 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_2__I2C2_SCL IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \ + 0x9b8, 3, MX51_I2C_PAD_CTRL) +#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \ + 0x9bc, 3, MX51_I2C_PAD_CTRL) +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) #endif /* __MACH_IOMUX_MX51_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h index 3887f3fe29d..15d59510f59 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __MACH_IOMUX_MXC91231_H__ diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index f2f73d31d5b..0880a4a1aed 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -89,6 +89,21 @@ struct pad_desc { #define PAD_CTL_SRE_FAST (1 << 0) #define PAD_CTL_SRE_SLOW (0 << 0) + +#define MX51_NUM_GPIO_PORT 4 + +#define GPIO_PIN_MASK 0x1f + +#define GPIO_PORT_SHIFT 5 +#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) + +#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) +#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) +#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) +#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) +#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) +#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) + /* * setups a single pad in the iomuxer */ diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index c4b40c35a6a..564ec9dbc93 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -44,12 +44,12 @@ */ #define CONSISTENT_DMA_SIZE SZ_8M -#elif defined(CONFIG_MX1_VIDEO) +#elif defined(CONFIG_MX1_VIDEO) || defined(CONFIG_VIDEO_MX2_HOSTSUPPORT) /* * Increase size of DMA-consistent memory region. * This is required for i.MX camera driver to capture at least four VGA frames. */ #define CONSISTENT_DMA_SIZE SZ_4M -#endif /* CONFIG_MX1_VIDEO */ +#endif /* CONFIG_MX1_VIDEO || CONFIG_VIDEO_MX2_HOSTSUPPORT */ #endif /* __ASM_ARCH_MXC_MEMORY_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mmc.h b/arch/arm/plat-mxc/include/mach/mmc.h index de2128dada5..29115f405af 100644 --- a/arch/arm/plat-mxc/include/mach/mmc.h +++ b/arch/arm/plat-mxc/include/mach/mmc.h @@ -31,6 +31,9 @@ struct imxmmc_platform_data { /* adjust slot voltage */ void (*setpower)(struct device *, unsigned int vdd); + + /* enable card detect using DAT3 */ + int dat3_card_detect; }; #endif diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index 5eba7e6785d..641b2461823 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -91,24 +91,24 @@ #define MX1_SIM_DATA_INT 16 #define MX1_RTC_INT 17 #define MX1_RTC_SAMINT 18 -#define MX1_UART2_MINT_PFERR 19 -#define MX1_UART2_MINT_RTS 20 -#define MX1_UART2_MINT_DTR 21 -#define MX1_UART2_MINT_UARTC 22 -#define MX1_UART2_MINT_TX 23 -#define MX1_UART2_MINT_RX 24 -#define MX1_UART1_MINT_PFERR 25 -#define MX1_UART1_MINT_RTS 26 -#define MX1_UART1_MINT_DTR 27 -#define MX1_UART1_MINT_UARTC 28 -#define MX1_UART1_MINT_TX 29 -#define MX1_UART1_MINT_RX 30 +#define MX1_INT_UART2PFERR 19 +#define MX1_INT_UART2RTS 20 +#define MX1_INT_UART2DTR 21 +#define MX1_INT_UART2UARTC 22 +#define MX1_INT_UART2TX 23 +#define MX1_INT_UART2RX 24 +#define MX1_INT_UART1PFERR 25 +#define MX1_INT_UART1RTS 26 +#define MX1_INT_UART1DTR 27 +#define MX1_INT_UART1UARTC 28 +#define MX1_INT_UART1TX 29 +#define MX1_INT_UART1RX 30 #define MX1_VOICE_DAC_INT 31 #define MX1_VOICE_ADC_INT 32 #define MX1_PEN_DATA_INT 33 #define MX1_PWM_INT 34 #define MX1_SDHC_INT 35 -#define MX1_I2C_INT 39 +#define MX1_INT_I2C 39 #define MX1_CSPI_INT 41 #define MX1_SSI_TX_INT 42 #define MX1_SSI_TX_ERR_INT 43 @@ -245,7 +245,7 @@ #define PEN_DATA_INT MX1_PEN_DATA_INT #define PWM_INT MX1_PWM_INT #define SDHC_INT MX1_SDHC_INT -#define I2C_INT MX1_I2C_INT +#define I2C_INT MX1_INT_I2C #define CSPI_INT MX1_CSPI_INT #define SSI_TX_INT MX1_SSI_TX_INT #define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 4eb6e334bda..4a6f800990f 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -11,6 +11,12 @@ #define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX25_AVIC_SIZE SZ_1M +#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) +#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000) +#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000) +#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000) +#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000) +#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000) #define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) @@ -27,22 +33,48 @@ IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \ IMX_IO_ADDRESS(x, MX25_AVIC)) +#define MX25_AIPS1_IO_ADDRESS(x) \ + (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT) + #define MX25_UART1_BASE_ADDR 0x43f90000 #define MX25_UART2_BASE_ADDR 0x43f94000 +#define MX25_AUDMUX_BASE_ADDR 0x43fb0000 +#define MX25_UART3_BASE_ADDR 0x5000c000 +#define MX25_UART4_BASE_ADDR 0x50008000 +#define MX25_UART5_BASE_ADDR 0x5002c000 +#define MX25_CSPI3_BASE_ADDR 0x50004000 +#define MX25_CSPI2_BASE_ADDR 0x50010000 #define MX25_FEC_BASE_ADDR 0x50038000 +#define MX25_SSI2_BASE_ADDR 0x50014000 +#define MX25_SSI1_BASE_ADDR 0x50034000 #define MX25_NFC_BASE_ADDR 0xbb000000 #define MX25_DRYICE_BASE_ADDR 0x53ffc000 #define MX25_LCDC_BASE_ADDR 0x53fbc000 +#define MX25_KPP_BASE_ADDR 0x43fa8000 +#define MX25_OTG_BASE_ADDR 0x53ff4000 +#define MX25_CSI_BASE_ADDR 0x53ff8000 -#define MX25_INT_DRYICE 25 -#define MX25_INT_FEC 57 -#define MX25_INT_NANDFC 33 -#define MX25_INT_LCDC 39 - -#if defined(IMX_NEEDS_DEPRECATED_SYMBOLS) -#define UART1_BASE_ADDR MX25_UART1_BASE_ADDR -#define UART2_BASE_ADDR MX25_UART2_BASE_ADDR -#endif +#define MX25_INT_CSPI3 0 +#define MX25_INT_I2C1 3 +#define MX25_INT_I2C2 4 +#define MX25_INT_UART4 5 +#define MX25_INT_I2C3 10 +#define MX25_INT_SSI2 11 +#define MX25_INT_SSI1 12 +#define MX25_INT_CSPI2 13 +#define MX25_INT_CSPI1 14 +#define MX25_INT_CSI 17 +#define MX25_INT_UART3 18 +#define MX25_INT_KPP 24 +#define MX25_INT_DRYICE 25 +#define MX25_INT_UART2 32 +#define MX25_INT_NANDFC 33 +#define MX25_INT_LCDC 39 +#define MX25_INT_UART5 40 +#define MX25_INT_CAN1 43 +#define MX25_INT_CAN2 44 +#define MX25_INT_UART1 45 +#define MX25_INT_FEC 57 #endif /* ifndef __MACH_MX25_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index bae9cd75bee..a8ab2e02a8c 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -48,7 +48,7 @@ #define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000) #define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000) #define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000) -#define MX27_I2C_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) +#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) #define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) #define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) #define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) @@ -150,7 +150,7 @@ static inline void mx27_setup_weimcs(size_t cs, #define MX27_INT_SDHC3 9 #define MX27_INT_SDHC2 10 #define MX27_INT_SDHC1 11 -#define MX27_INT_I2C 12 +#define MX27_INT_I2C1 12 #define MX27_INT_SSI2 13 #define MX27_INT_SSI1 14 #define MX27_INT_CSPI2 15 diff --git a/arch/arm/plat-mxc/include/mach/mx2_cam.h b/arch/arm/plat-mxc/include/mach/mx2_cam.h new file mode 100644 index 00000000000..3c080a32dbf --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx2_cam.h @@ -0,0 +1,46 @@ +/* + * mx2-cam.h - i.MX27/i.MX25 camera driver header file + * + * Copyright (C) 2003, Intel Corporation + * Copyright (C) 2008, Sascha Hauer <s.hauer@pengutronix.de> + * Copyright (C) 2010, Baruch Siach <baruch@tkos.co.il> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_MX2_CAM_H_ +#define __MACH_MX2_CAM_H_ + +#define MX2_CAMERA_SWAP16 (1 << 0) +#define MX2_CAMERA_EXT_VSYNC (1 << 1) +#define MX2_CAMERA_CCIR (1 << 2) +#define MX2_CAMERA_CCIR_INTERLACE (1 << 3) +#define MX2_CAMERA_HSYNC_HIGH (1 << 4) +#define MX2_CAMERA_GATED_CLOCK (1 << 5) +#define MX2_CAMERA_INV_DATA (1 << 6) +#define MX2_CAMERA_PCLK_SAMPLE_RISING (1 << 7) +#define MX2_CAMERA_PACK_DIR_MSB (1 << 8) + +/** + * struct mx2_camera_platform_data - optional platform data for mx2_camera + * @flags: any combination of MX2_CAMERA_* + * @clk: clock rate of the csi block / 2 + */ +struct mx2_camera_platform_data { + unsigned long flags; + unsigned long clk; +}; + +#endif /* __MACH_MX2_CAM_H_ */ diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index fb90e119c2b..afee3ab9d62 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -23,7 +23,7 @@ #define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000) #define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000) #define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) -#define MX31_I2C_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) +#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) #define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) #define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) #define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) @@ -145,7 +145,7 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_FIRI 7 #define MX31_INT_MMC_SDHC2 8 #define MX31_INT_MMC_SDHC1 9 -#define MX31_INT_I2C 10 +#define MX31_INT_I2C1 10 #define MX31_INT_SSI2 11 #define MX31_INT_SSI1 12 #define MX31_INT_CSPI2 13 diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 526a55842ae..af3038c12e3 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -18,7 +18,7 @@ #define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000) #define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000) #define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000) -#define MX35_I2C_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) +#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) #define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000) #define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000) #define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000) @@ -60,6 +60,8 @@ #define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000) #define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000) #define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000) +#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000) +#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) #define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) #define MX35_OTG_BASE_ADDR 0x53ff4000 @@ -123,7 +125,7 @@ #define MX35_INT_MMC_SDHC1 7 #define MX35_INT_MMC_SDHC2 8 #define MX35_INT_MMC_SDHC3 9 -#define MX35_INT_I2C 10 +#define MX35_INT_I2C1 10 #define MX35_INT_SSI1 11 #define MX35_INT_SSI2 12 #define MX35_INT_CSPI2 13 diff --git a/arch/arm/plat-mxc/include/mach/mx3_camera.h b/arch/arm/plat-mxc/include/mach/mx3_camera.h index 36d7ff27b5e..f226ee3777e 100644 --- a/arch/arm/plat-mxc/include/mach/mx3_camera.h +++ b/arch/arm/plat-mxc/include/mach/mx3_camera.h @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef _MX3_CAMERA_H_ diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h index 5182b986b78..0ca3101ebf3 100644 --- a/arch/arm/plat-mxc/include/mach/mxc91231.h +++ b/arch/arm/plat-mxc/include/mach/mxc91231.h @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __MACH_MXC91231_H__ #define __MACH_MXC91231_H__ diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h index 5d2d21d414e..04c0d060d81 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_nand.h +++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h @@ -20,9 +20,13 @@ #ifndef __ASM_ARCH_NAND_H #define __ASM_ARCH_NAND_H +#include <linux/mtd/partitions.h> + struct mxc_nand_platform_data { - int width; /* data bus width in bytes */ - int hw_ecc:1; /* 0 if supress hardware ECC */ - int flash_bbt:1; /* set to 1 to use a flash based bbt */ + unsigned int width; /* data bus width in bytes */ + unsigned int hw_ecc:1; /* 0 if supress hardware ECC */ + unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */ + struct mtd_partition *parts; /* partition table */ + int nr_parts; /* size of parts */ }; #endif /* __ASM_ARCH_NAND_H */ diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h index ef00199568d..4acd1143a9b 100644 --- a/arch/arm/plat-mxc/include/mach/system.h +++ b/arch/arm/plat-mxc/include/mach/system.h @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_ARCH_MXC_SYSTEM_H__ diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h index 024416ed11c..2d9624697cc 100644 --- a/arch/arm/plat-mxc/include/mach/timex.h +++ b/arch/arm/plat-mxc/include/mach/timex.h @@ -11,10 +11,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_ARCH_MXC_TIMEX_H__ diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index b6d3d0fddc4..d9bd37e4667 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__ #define __ASM_ARCH_MXC_UNCOMPRESS_H__ diff --git a/arch/arm/plat-mxc/include/mach/vmalloc.h b/arch/arm/plat-mxc/include/mach/vmalloc.h index 44243a27843..ef6379c474b 100644 --- a/arch/arm/plat-mxc/include/mach/vmalloc.h +++ b/arch/arm/plat-mxc/include/mach/vmalloc.h @@ -11,10 +11,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_ARCH_MXC_VMALLOC_H__ diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c index 778ddfe57d8..7331f2ace5f 100644 --- a/arch/arm/plat-mxc/irq.c +++ b/arch/arm/plat-mxc/irq.c @@ -142,9 +142,6 @@ void __init mxc_init_irq(void __iomem *irqbase) for (i = 0; i < 8; i++) __raw_writel(0, avic_base + AVIC_NIPRIORITY(i)); - /* init architectures chained interrupt handler */ - mxc_register_gpios(); - #ifdef CONFIG_FIQ /* Initialize FIQ */ init_FIQ(); diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index 97f42799fa5..925bce4607e 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c @@ -14,10 +14,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/kernel.h> diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index 9b86d2a60d4..b3da9aad429 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c @@ -145,8 +145,6 @@ void __init tzic_init_irq(void __iomem *irqbase) set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID); } - mxc_register_gpios(); - pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); } diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig index bdbc9d30541..27e2acce3c3 100644 --- a/drivers/media/video/Kconfig +++ b/drivers/media/video/Kconfig @@ -969,6 +969,19 @@ config VIDEO_OMAP2 ---help--- This is a v4l2 driver for the TI OMAP2 camera capture interface +config VIDEO_MX2_HOSTSUPPORT + bool + +config VIDEO_MX2 + tristate "i.MX27/i.MX25 Camera Sensor Interface driver" + depends on VIDEO_DEV && SOC_CAMERA && (MACH_MX27 || ARCH_MX25) + select VIDEOBUF_DMA_CONTIG + select VIDEO_MX2_HOSTSUPPORT + ---help--- + This is a v4l2 driver for the i.MX27 and the i.MX25 Camera Sensor + Interface + + # # USB Multimedia device configuration # diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile index cc93859d316..b08bd2b65cd 100644 --- a/drivers/media/video/Makefile +++ b/drivers/media/video/Makefile @@ -162,6 +162,7 @@ obj-$(CONFIG_SOC_CAMERA) += soc_camera.o soc_mediabus.o obj-$(CONFIG_SOC_CAMERA_PLATFORM) += soc_camera_platform.o # soc-camera host drivers have to be linked after camera drivers obj-$(CONFIG_VIDEO_MX1) += mx1_camera.o +obj-$(CONFIG_VIDEO_MX2) += mx2_camera.o obj-$(CONFIG_VIDEO_MX3) += mx3_camera.o obj-$(CONFIG_VIDEO_PXA27x) += pxa_camera.o obj-$(CONFIG_VIDEO_SH_MOBILE_CEU) += sh_mobile_ceu_camera.o diff --git a/drivers/media/video/mx2_camera.c b/drivers/media/video/mx2_camera.c new file mode 100644 index 00000000000..026bef0ba40 --- /dev/null +++ b/drivers/media/video/mx2_camera.c @@ -0,0 +1,1513 @@ +/* + * V4L2 Driver for i.MX27/i.MX25 camera host + * + * Copyright (C) 2008, Sascha Hauer, Pengutronix + * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/slab.h> +#include <linux/dma-mapping.h> +#include <linux/errno.h> +#include <linux/fs.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/moduleparam.h> +#include <linux/time.h> +#include <linux/version.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/mutex.h> +#include <linux/clk.h> + +#include <media/v4l2-common.h> +#include <media/v4l2-dev.h> +#include <media/videobuf-dma-contig.h> +#include <media/soc_camera.h> +#include <media/soc_mediabus.h> + +#include <linux/videodev2.h> + +#include <mach/mx2_cam.h> +#ifdef CONFIG_MACH_MX27 +#include <mach/dma-mx1-mx2.h> +#endif +#include <mach/hardware.h> + +#include <asm/dma.h> + +#define MX2_CAM_DRV_NAME "mx2-camera" +#define MX2_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) +#define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera" + +/* reset values */ +#define CSICR1_RESET_VAL 0x40000800 +#define CSICR2_RESET_VAL 0x0 +#define CSICR3_RESET_VAL 0x0 + +/* csi control reg 1 */ +#define CSICR1_SWAP16_EN (1 << 31) +#define CSICR1_EXT_VSYNC (1 << 30) +#define CSICR1_EOF_INTEN (1 << 29) +#define CSICR1_PRP_IF_EN (1 << 28) +#define CSICR1_CCIR_MODE (1 << 27) +#define CSICR1_COF_INTEN (1 << 26) +#define CSICR1_SF_OR_INTEN (1 << 25) +#define CSICR1_RF_OR_INTEN (1 << 24) +#define CSICR1_STATFF_LEVEL (3 << 22) +#define CSICR1_STATFF_INTEN (1 << 21) +#define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */ +#define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */ +#define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */ +#define CSICR1_RXFF_INTEN (1 << 18) +#define CSICR1_SOF_POL (1 << 17) +#define CSICR1_SOF_INTEN (1 << 16) +#define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12) +#define CSICR1_HSYNC_POL (1 << 11) +#define CSICR1_CCIR_EN (1 << 10) +#define CSICR1_MCLKEN (1 << 9) +#define CSICR1_FCC (1 << 8) +#define CSICR1_PACK_DIR (1 << 7) +#define CSICR1_CLR_STATFIFO (1 << 6) +#define CSICR1_CLR_RXFIFO (1 << 5) +#define CSICR1_GCLK_MODE (1 << 4) +#define CSICR1_INV_DATA (1 << 3) +#define CSICR1_INV_PCLK (1 << 2) +#define CSICR1_REDGE (1 << 1) + +#define SHIFT_STATFF_LEVEL 22 +#define SHIFT_RXFF_LEVEL 19 +#define SHIFT_MCLKDIV 12 + +/* control reg 3 */ +#define CSICR3_FRMCNT (0xFFFF << 16) +#define CSICR3_FRMCNT_RST (1 << 15) +#define CSICR3_DMA_REFLASH_RFF (1 << 14) +#define CSICR3_DMA_REFLASH_SFF (1 << 13) +#define CSICR3_DMA_REQ_EN_RFF (1 << 12) +#define CSICR3_DMA_REQ_EN_SFF (1 << 11) +#define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */ +#define CSICR3_CSI_SUP (1 << 3) +#define CSICR3_ZERO_PACK_EN (1 << 2) +#define CSICR3_ECC_INT_EN (1 << 1) +#define CSICR3_ECC_AUTO_EN (1 << 0) + +#define SHIFT_FRMCNT 16 + +/* csi status reg */ +#define CSISR_SFF_OR_INT (1 << 25) +#define CSISR_RFF_OR_INT (1 << 24) +#define CSISR_STATFF_INT (1 << 21) +#define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */ +#define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */ +#define CSISR_RXFF_INT (1 << 18) +#define CSISR_EOF_INT (1 << 17) +#define CSISR_SOF_INT (1 << 16) +#define CSISR_F2_INT (1 << 15) +#define CSISR_F1_INT (1 << 14) +#define CSISR_COF_INT (1 << 13) +#define CSISR_ECC_INT (1 << 1) +#define CSISR_DRDY (1 << 0) + +#define CSICR1 0x00 +#define CSICR2 0x04 +#define CSISR (cpu_is_mx27() ? 0x08 : 0x18) +#define CSISTATFIFO 0x0c +#define CSIRFIFO 0x10 +#define CSIRXCNT 0x14 +#define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08) +#define CSIDMASA_STATFIFO 0x20 +#define CSIDMATA_STATFIFO 0x24 +#define CSIDMASA_FB1 0x28 +#define CSIDMASA_FB2 0x2c +#define CSIFBUF_PARA 0x30 +#define CSIIMAG_PARA 0x34 + +/* EMMA PrP */ +#define PRP_CNTL 0x00 +#define PRP_INTR_CNTL 0x04 +#define PRP_INTRSTATUS 0x08 +#define PRP_SOURCE_Y_PTR 0x0c +#define PRP_SOURCE_CB_PTR 0x10 +#define PRP_SOURCE_CR_PTR 0x14 +#define PRP_DEST_RGB1_PTR 0x18 +#define PRP_DEST_RGB2_PTR 0x1c +#define PRP_DEST_Y_PTR 0x20 +#define PRP_DEST_CB_PTR 0x24 +#define PRP_DEST_CR_PTR 0x28 +#define PRP_SRC_FRAME_SIZE 0x2c +#define PRP_DEST_CH1_LINE_STRIDE 0x30 +#define PRP_SRC_PIXEL_FORMAT_CNTL 0x34 +#define PRP_CH1_PIXEL_FORMAT_CNTL 0x38 +#define PRP_CH1_OUT_IMAGE_SIZE 0x3c +#define PRP_CH2_OUT_IMAGE_SIZE 0x40 +#define PRP_SRC_LINE_STRIDE 0x44 +#define PRP_CSC_COEF_012 0x48 +#define PRP_CSC_COEF_345 0x4c +#define PRP_CSC_COEF_678 0x50 +#define PRP_CH1_RZ_HORI_COEF1 0x54 +#define PRP_CH1_RZ_HORI_COEF2 0x58 +#define PRP_CH1_RZ_HORI_VALID 0x5c +#define PRP_CH1_RZ_VERT_COEF1 0x60 +#define PRP_CH1_RZ_VERT_COEF2 0x64 +#define PRP_CH1_RZ_VERT_VALID 0x68 +#define PRP_CH2_RZ_HORI_COEF1 0x6c +#define PRP_CH2_RZ_HORI_COEF2 0x70 +#define PRP_CH2_RZ_HORI_VALID 0x74 +#define PRP_CH2_RZ_VERT_COEF1 0x78 +#define PRP_CH2_RZ_VERT_COEF2 0x7c +#define PRP_CH2_RZ_VERT_VALID 0x80 + +#define PRP_CNTL_CH1EN (1 << 0) +#define PRP_CNTL_CH2EN (1 << 1) +#define PRP_CNTL_CSIEN (1 << 2) +#define PRP_CNTL_DATA_IN_YUV420 (0 << 3) +#define PRP_CNTL_DATA_IN_YUV422 (1 << 3) +#define PRP_CNTL_DATA_IN_RGB16 (2 << 3) +#define PRP_CNTL_DATA_IN_RGB32 (3 << 3) +#define PRP_CNTL_CH1_OUT_RGB8 (0 << 5) +#define PRP_CNTL_CH1_OUT_RGB16 (1 << 5) +#define PRP_CNTL_CH1_OUT_RGB32 (2 << 5) +#define PRP_CNTL_CH1_OUT_YUV422 (3 << 5) +#define PRP_CNTL_CH2_OUT_YUV420 (0 << 7) +#define PRP_CNTL_CH2_OUT_YUV422 (1 << 7) +#define PRP_CNTL_CH2_OUT_YUV444 (2 << 7) +#define PRP_CNTL_CH1_LEN (1 << 9) +#define PRP_CNTL_CH2_LEN (1 << 10) +#define PRP_CNTL_SKIP_FRAME (1 << 11) +#define PRP_CNTL_SWRST (1 << 12) +#define PRP_CNTL_CLKEN (1 << 13) +#define PRP_CNTL_WEN (1 << 14) +#define PRP_CNTL_CH1BYP (1 << 15) +#define PRP_CNTL_IN_TSKIP(x) ((x) << 16) +#define PRP_CNTL_CH1_TSKIP(x) ((x) << 19) +#define PRP_CNTL_CH2_TSKIP(x) ((x) << 22) +#define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25) +#define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27) +#define PRP_CNTL_CH2B1EN (1 << 29) +#define PRP_CNTL_CH2B2EN (1 << 30) +#define PRP_CNTL_CH2FEN (1 << 31) + +/* IRQ Enable and status register */ +#define PRP_INTR_RDERR (1 << 0) +#define PRP_INTR_CH1WERR (1 << 1) +#define PRP_INTR_CH2WERR (1 << 2) +#define PRP_INTR_CH1FC (1 << 3) +#define PRP_INTR_CH2FC (1 << 5) +#define PRP_INTR_LBOVF (1 << 7) +#define PRP_INTR_CH2OVF (1 << 8) + +#define mx27_camera_emma(pcdev) (cpu_is_mx27() && pcdev->use_emma) + +#define MAX_VIDEO_MEM 16 + +struct mx2_camera_dev { + struct device *dev; + struct soc_camera_host soc_host; + struct soc_camera_device *icd; + struct clk *clk_csi, *clk_emma; + + unsigned int irq_csi, irq_emma; + void __iomem *base_csi, *base_emma; + unsigned long base_dma; + + struct mx2_camera_platform_data *pdata; + struct resource *res_csi, *res_emma; + unsigned long platform_flags; + + struct list_head capture; + struct list_head active_bufs; + + spinlock_t lock; + + int dma; + struct mx2_buffer *active; + struct mx2_buffer *fb1_active; + struct mx2_buffer *fb2_active; + + int use_emma; + + u32 csicr1; + + void *discard_buffer; + dma_addr_t discard_buffer_dma; + size_t discard_size; +}; + +/* buffer for one video frame */ +struct mx2_buffer { + /* common v4l buffer stuff -- must be first */ + struct videobuf_buffer vb; + + enum v4l2_mbus_pixelcode code; + + int bufnum; +}; + +static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev) +{ + unsigned long flags; + + clk_disable(pcdev->clk_csi); + writel(0, pcdev->base_csi + CSICR1); + if (mx27_camera_emma(pcdev)) { + writel(0, pcdev->base_emma + PRP_CNTL); + } else if (cpu_is_mx25()) { + spin_lock_irqsave(&pcdev->lock, flags); + pcdev->fb1_active = NULL; + pcdev->fb2_active = NULL; + writel(0, pcdev->base_csi + CSIDMASA_FB1); + writel(0, pcdev->base_csi + CSIDMASA_FB2); + spin_unlock_irqrestore(&pcdev->lock, flags); + } +} + +/* + * The following two functions absolutely depend on the fact, that + * there can be only one camera on mx2 camera sensor interface + */ +static int mx2_camera_add_device(struct soc_camera_device *icd) +{ + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct mx2_camera_dev *pcdev = ici->priv; + int ret; + u32 csicr1; + + if (pcdev->icd) + return -EBUSY; + + ret = clk_enable(pcdev->clk_csi); + if (ret < 0) + return ret; + + csicr1 = CSICR1_MCLKEN; + + if (mx27_camera_emma(pcdev)) { + csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC | + CSICR1_RXFF_LEVEL(0); + } else if (cpu_is_mx27()) + csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2); + + pcdev->csicr1 = csicr1; + writel(pcdev->csicr1, pcdev->base_csi + CSICR1); + + pcdev->icd = icd; + + dev_info(icd->dev.parent, "Camera driver attached to camera %d\n", + icd->devnum); + + return 0; +} + +static void mx2_camera_remove_device(struct soc_camera_device *icd) +{ + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct mx2_camera_dev *pcdev = ici->priv; + + BUG_ON(icd != pcdev->icd); + + dev_info(icd->dev.parent, "Camera driver detached from camera %d\n", + icd->devnum); + + mx2_camera_deactivate(pcdev); + + if (pcdev->discard_buffer) { + dma_free_coherent(ici->v4l2_dev.dev, pcdev->discard_size, + pcdev->discard_buffer, + pcdev->discard_buffer_dma); + pcdev->discard_buffer = NULL; + } + + pcdev->icd = NULL; +} + +#ifdef CONFIG_MACH_MX27 +static void mx27_camera_dma_enable(struct mx2_camera_dev *pcdev) +{ + u32 tmp; + + imx_dma_enable(pcdev->dma); + + tmp = readl(pcdev->base_csi + CSICR1); + tmp |= CSICR1_RF_OR_INTEN; + writel(tmp, pcdev->base_csi + CSICR1); +} + +static irqreturn_t mx27_camera_irq(int irq_csi, void *data) +{ + struct mx2_camera_dev *pcdev = data; + u32 status = readl(pcdev->base_csi + CSISR); + + if (status & CSISR_SOF_INT && pcdev->active) { + u32 tmp; + + tmp = readl(pcdev->base_csi + CSICR1); + writel(tmp | CSICR1_CLR_RXFIFO, pcdev->base_csi + CSICR1); + mx27_camera_dma_enable(pcdev); + } + + writel(CSISR_SOF_INT | CSISR_RFF_OR_INT, pcdev->base_csi + CSISR); + + return IRQ_HANDLED; +} +#else +static irqreturn_t mx27_camera_irq(int irq_csi, void *data) +{ + return IRQ_NONE; +} +#endif /* CONFIG_MACH_MX27 */ + +static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb, + int state) +{ + struct videobuf_buffer *vb; + struct mx2_buffer *buf; + struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active : + &pcdev->fb2_active; + u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2; + unsigned long flags; + + spin_lock_irqsave(&pcdev->lock, flags); + + vb = &(*fb_active)->vb; + dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + vb, vb->baddr, vb->bsize); + + vb->state = state; + do_gettimeofday(&vb->ts); + vb->field_count++; + + wake_up(&vb->done); + + if (list_empty(&pcdev->capture)) { + buf = NULL; + writel(0, pcdev->base_csi + fb_reg); + } else { + buf = list_entry(pcdev->capture.next, struct mx2_buffer, + vb.queue); + vb = &buf->vb; + list_del(&vb->queue); + vb->state = VIDEOBUF_ACTIVE; + writel(videobuf_to_dma_contig(vb), pcdev->base_csi + fb_reg); + } + + *fb_active = buf; + + spin_unlock_irqrestore(&pcdev->lock, flags); +} + +static irqreturn_t mx25_camera_irq(int irq_csi, void *data) +{ + struct mx2_camera_dev *pcdev = data; + u32 status = readl(pcdev->base_csi + CSISR); + + if (status & CSISR_DMA_TSF_FB1_INT) + mx25_camera_frame_done(pcdev, 1, VIDEOBUF_DONE); + else if (status & CSISR_DMA_TSF_FB2_INT) + mx25_camera_frame_done(pcdev, 2, VIDEOBUF_DONE); + + /* FIXME: handle CSISR_RFF_OR_INT */ + + writel(status, pcdev->base_csi + CSISR); + + return IRQ_HANDLED; +} + +/* + * Videobuf operations + */ +static int mx2_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, + unsigned int *size) +{ + struct soc_camera_device *icd = vq->priv_data; + int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, + icd->current_fmt->host_fmt); + + dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size); + + if (bytes_per_line < 0) + return bytes_per_line; + + *size = bytes_per_line * icd->user_height; + + if (0 == *count) + *count = 32; + if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024) + *count = (MAX_VIDEO_MEM * 1024 * 1024) / *size; + + return 0; +} + +static void free_buffer(struct videobuf_queue *vq, struct mx2_buffer *buf) +{ + struct soc_camera_device *icd = vq->priv_data; + struct videobuf_buffer *vb = &buf->vb; + + dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + vb, vb->baddr, vb->bsize); + + /* + * This waits until this buffer is out of danger, i.e., until it is no + * longer in STATE_QUEUED or STATE_ACTIVE + */ + videobuf_waiton(vb, 0, 0); + + videobuf_dma_contig_free(vq, vb); + dev_dbg(&icd->dev, "%s freed\n", __func__); + + vb->state = VIDEOBUF_NEEDS_INIT; +} + +static int mx2_videobuf_prepare(struct videobuf_queue *vq, + struct videobuf_buffer *vb, enum v4l2_field field) +{ + struct soc_camera_device *icd = vq->priv_data; + struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); + int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, + icd->current_fmt->host_fmt); + int ret = 0; + + dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + vb, vb->baddr, vb->bsize); + + if (bytes_per_line < 0) + return bytes_per_line; + +#ifdef DEBUG + /* + * This can be useful if you want to see if we actually fill + * the buffer with something + */ + memset((void *)vb->baddr, 0xaa, vb->bsize); +#endif + + if (buf->code != icd->current_fmt->code || + vb->width != icd->user_width || + vb->height != icd->user_height || + vb->field != field) { + buf->code = icd->current_fmt->code; + vb->width = icd->user_width; + vb->height = icd->user_height; + vb->field = field; + vb->state = VIDEOBUF_NEEDS_INIT; + } + + vb->size = bytes_per_line * vb->height; + if (vb->baddr && vb->bsize < vb->size) { + ret = -EINVAL; + goto out; + } + + if (vb->state == VIDEOBUF_NEEDS_INIT) { + ret = videobuf_iolock(vq, vb, NULL); + if (ret) + goto fail; + + vb->state = VIDEOBUF_PREPARED; + } + + return 0; + +fail: + free_buffer(vq, buf); +out: + return ret; +} + +static void mx2_videobuf_queue(struct videobuf_queue *vq, + struct videobuf_buffer *vb) +{ + struct soc_camera_device *icd = vq->priv_data; + struct soc_camera_host *ici = + to_soc_camera_host(icd->dev.parent); + struct mx2_camera_dev *pcdev = ici->priv; + struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); + unsigned long flags; + + dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + vb, vb->baddr, vb->bsize); + + spin_lock_irqsave(&pcdev->lock, flags); + + vb->state = VIDEOBUF_QUEUED; + list_add_tail(&vb->queue, &pcdev->capture); + + if (mx27_camera_emma(pcdev)) { + goto out; +#ifdef CONFIG_MACH_MX27 + } else if (cpu_is_mx27()) { + int ret; + + if (pcdev->active == NULL) { + ret = imx_dma_setup_single(pcdev->dma, + videobuf_to_dma_contig(vb), vb->size, + (u32)pcdev->base_dma + 0x10, + DMA_MODE_READ); + if (ret) { + vb->state = VIDEOBUF_ERROR; + wake_up(&vb->done); + goto out; + } + + vb->state = VIDEOBUF_ACTIVE; + pcdev->active = buf; + } +#endif + } else { /* cpu_is_mx25() */ + u32 csicr3, dma_inten = 0; + + if (pcdev->fb1_active == NULL) { + writel(videobuf_to_dma_contig(vb), + pcdev->base_csi + CSIDMASA_FB1); + pcdev->fb1_active = buf; + dma_inten = CSICR1_FB1_DMA_INTEN; + } else if (pcdev->fb2_active == NULL) { + writel(videobuf_to_dma_contig(vb), + pcdev->base_csi + CSIDMASA_FB2); + pcdev->fb2_active = buf; + dma_inten = CSICR1_FB2_DMA_INTEN; + } + + if (dma_inten) { + list_del(&vb->queue); + vb->state = VIDEOBUF_ACTIVE; + + csicr3 = readl(pcdev->base_csi + CSICR3); + + /* Reflash DMA */ + writel(csicr3 | CSICR3_DMA_REFLASH_RFF, + pcdev->base_csi + CSICR3); + + /* clear & enable interrupts */ + writel(dma_inten, pcdev->base_csi + CSISR); + pcdev->csicr1 |= dma_inten; + writel(pcdev->csicr1, pcdev->base_csi + CSICR1); + + /* enable DMA */ + csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1); + writel(csicr3, pcdev->base_csi + CSICR3); + } + } + +out: + spin_unlock_irqrestore(&pcdev->lock, flags); +} + +static void mx2_videobuf_release(struct videobuf_queue *vq, + struct videobuf_buffer *vb) +{ + struct soc_camera_device *icd = vq->priv_data; + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct mx2_camera_dev *pcdev = ici->priv; + struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); + unsigned long flags; + +#ifdef DEBUG + dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + vb, vb->baddr, vb->bsize); + + switch (vb->state) { + case VIDEOBUF_ACTIVE: + dev_info(&icd->dev, "%s (active)\n", __func__); + break; + case VIDEOBUF_QUEUED: + dev_info(&icd->dev, "%s (queued)\n", __func__); + break; + case VIDEOBUF_PREPARED: + dev_info(&icd->dev, "%s (prepared)\n", __func__); + break; + default: + dev_info(&icd->dev, "%s (unknown) %d\n", __func__, + vb->state); + break; + } +#endif + + /* + * Terminate only queued but inactive buffers. Active buffers are + * released when they become inactive after videobuf_waiton(). + * + * FIXME: implement forced termination of active buffers, so that the + * user won't get stuck in an uninterruptible state. This requires a + * specific handling for each of the three DMA types that this driver + * supports. + */ + spin_lock_irqsave(&pcdev->lock, flags); + if (vb->state == VIDEOBUF_QUEUED) { + list_del(&vb->queue); + vb->state = VIDEOBUF_ERROR; + } + spin_unlock_irqrestore(&pcdev->lock, flags); + + free_buffer(vq, buf); +} + +static struct videobuf_queue_ops mx2_videobuf_ops = { + .buf_setup = mx2_videobuf_setup, + .buf_prepare = mx2_videobuf_prepare, + .buf_queue = mx2_videobuf_queue, + .buf_release = mx2_videobuf_release, +}; + +static void mx2_camera_init_videobuf(struct videobuf_queue *q, + struct soc_camera_device *icd) +{ + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct mx2_camera_dev *pcdev = ici->priv; + + videobuf_queue_dma_contig_init(q, &mx2_videobuf_ops, pcdev->dev, + &pcdev->lock, V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_NONE, sizeof(struct mx2_buffer), icd); +} + +#define MX2_BUS_FLAGS (SOCAM_DATAWIDTH_8 | \ + SOCAM_MASTER | \ + SOCAM_VSYNC_ACTIVE_HIGH | \ + SOCAM_VSYNC_ACTIVE_LOW | \ + SOCAM_HSYNC_ACTIVE_HIGH | \ + SOCAM_HSYNC_ACTIVE_LOW | \ + SOCAM_PCLK_SAMPLE_RISING | \ + SOCAM_PCLK_SAMPLE_FALLING | \ + SOCAM_DATA_ACTIVE_HIGH | \ + SOCAM_DATA_ACTIVE_LOW) + +static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev) +{ + u32 cntl; + int count = 0; + + cntl = readl(pcdev->base_emma + PRP_CNTL); + writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL); + while (count++ < 100) { + if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST)) + return 0; + barrier(); + udelay(1); + } + + return -ETIMEDOUT; +} + +static void mx27_camera_emma_buf_init(struct soc_camera_device *icd, + int bytesperline) +{ + struct soc_camera_host *ici = + to_soc_camera_host(icd->dev.parent); + struct mx2_camera_dev *pcdev = ici->priv; + + writel(pcdev->discard_buffer_dma, + pcdev->base_emma + PRP_DEST_RGB1_PTR); + writel(pcdev->discard_buffer_dma, + pcdev->base_emma + PRP_DEST_RGB2_PTR); + + /* + * We only use the EMMA engine to get rid of the broken + * DMA Engine. No color space consversion at the moment. + * We adjust incoming and outgoing pixelformat to rgb16 + * and adjust the bytesperline accordingly. + */ + writel(PRP_CNTL_CH1EN | + PRP_CNTL_CSIEN | + PRP_CNTL_DATA_IN_RGB16 | + PRP_CNTL_CH1_OUT_RGB16 | + PRP_CNTL_CH1_LEN | + PRP_CNTL_CH1BYP | + PRP_CNTL_CH1_TSKIP(0) | + PRP_CNTL_IN_TSKIP(0), + pcdev->base_emma + PRP_CNTL); + + writel(((bytesperline >> 1) << 16) | icd->user_height, + pcdev->base_emma + PRP_SRC_FRAME_SIZE); + writel(((bytesperline >> 1) << 16) | icd->user_height, + pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE); + writel(bytesperline, + pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE); + writel(0x2ca00565, /* RGB565 */ + pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL); + writel(0x2ca00565, /* RGB565 */ + pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL); + + /* Enable interrupts */ + writel(PRP_INTR_RDERR | + PRP_INTR_CH1WERR | + PRP_INTR_CH2WERR | + PRP_INTR_CH1FC | + PRP_INTR_CH2FC | + PRP_INTR_LBOVF | + PRP_INTR_CH2OVF, + pcdev->base_emma + PRP_INTR_CNTL); +} + +static int mx2_camera_set_bus_param(struct soc_camera_device *icd, + __u32 pixfmt) +{ + struct soc_camera_host *ici = + to_soc_camera_host(icd->dev.parent); + struct mx2_camera_dev *pcdev = ici->priv; + unsigned long camera_flags, common_flags; + int ret = 0; + int bytesperline; + u32 csicr1 = pcdev->csicr1; + + camera_flags = icd->ops->query_bus_param(icd); + + common_flags = soc_camera_bus_param_compatible(camera_flags, + MX2_BUS_FLAGS); + if (!common_flags) + return -EINVAL; + + if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) && + (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) { + if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH) + common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW; + else + common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH; + } + + if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) && + (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) { + if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING) + common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING; + else + common_flags &= ~SOCAM_PCLK_SAMPLE_RISING; + } + + ret = icd->ops->set_bus_param(icd, common_flags); + if (ret < 0) + return ret; + + if (common_flags & SOCAM_PCLK_SAMPLE_FALLING) + csicr1 |= CSICR1_INV_PCLK; + if (common_flags & SOCAM_VSYNC_ACTIVE_HIGH) + csicr1 |= CSICR1_SOF_POL; + if (common_flags & SOCAM_HSYNC_ACTIVE_HIGH) + csicr1 |= CSICR1_HSYNC_POL; + if (pcdev->platform_flags & MX2_CAMERA_SWAP16) + csicr1 |= CSICR1_SWAP16_EN; + if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC) + csicr1 |= CSICR1_EXT_VSYNC; + if (pcdev->platform_flags & MX2_CAMERA_CCIR) + csicr1 |= CSICR1_CCIR_EN; + if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE) + csicr1 |= CSICR1_CCIR_MODE; + if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK) + csicr1 |= CSICR1_GCLK_MODE; + if (pcdev->platform_flags & MX2_CAMERA_INV_DATA) + csicr1 |= CSICR1_INV_DATA; + if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB) + csicr1 |= CSICR1_PACK_DIR; + + pcdev->csicr1 = csicr1; + + bytesperline = soc_mbus_bytes_per_line(icd->user_width, + icd->current_fmt->host_fmt); + if (bytesperline < 0) + return bytesperline; + + if (mx27_camera_emma(pcdev)) { + ret = mx27_camera_emma_prp_reset(pcdev); + if (ret) + return ret; + + if (pcdev->discard_buffer) + dma_free_coherent(ici->v4l2_dev.dev, + pcdev->discard_size, pcdev->discard_buffer, + pcdev->discard_buffer_dma); + + /* + * I didn't manage to properly enable/disable the prp + * on a per frame basis during running transfers, + * thus we allocate a buffer here and use it to + * discard frames when no buffer is available. + * Feel free to work on this ;) + */ + pcdev->discard_size = icd->user_height * bytesperline; + pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev, + pcdev->discard_size, &pcdev->discard_buffer_dma, + GFP_KERNEL); + if (!pcdev->discard_buffer) + return -ENOMEM; + + mx27_camera_emma_buf_init(icd, bytesperline); + } else if (cpu_is_mx25()) { + writel((bytesperline * icd->user_height) >> 2, + pcdev->base_csi + CSIRXCNT); + writel((bytesperline << 16) | icd->user_height, + pcdev->base_csi + CSIIMAG_PARA); + } + + writel(pcdev->csicr1, pcdev->base_csi + CSICR1); + + return 0; +} + +static int mx2_camera_set_crop(struct soc_camera_device *icd, + struct v4l2_crop *a) +{ + struct v4l2_rect *rect = &a->c; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + struct v4l2_mbus_framefmt mf; + int ret; + + soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096); + soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096); + + ret = v4l2_subdev_call(sd, video, s_crop, a); + if (ret < 0) + return ret; + + /* The capture device might have changed its output */ + ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); + if (ret < 0) + return ret; + + dev_dbg(icd->dev.parent, "Sensor cropped %dx%d\n", + mf.width, mf.height); + + icd->user_width = mf.width; + icd->user_height = mf.height; + + return ret; +} + +static int mx2_camera_set_fmt(struct soc_camera_device *icd, + struct v4l2_format *f) +{ + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct mx2_camera_dev *pcdev = ici->priv; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + const struct soc_camera_format_xlate *xlate; + struct v4l2_pix_format *pix = &f->fmt.pix; + struct v4l2_mbus_framefmt mf; + int ret; + + xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); + if (!xlate) { + dev_warn(icd->dev.parent, "Format %x not found\n", + pix->pixelformat); + return -EINVAL; + } + + /* eMMA can only do RGB565 */ + if (mx27_camera_emma(pcdev) && pix->pixelformat != V4L2_PIX_FMT_RGB565) + return -EINVAL; + + mf.width = pix->width; + mf.height = pix->height; + mf.field = pix->field; + mf.colorspace = pix->colorspace; + mf.code = xlate->code; + + ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); + if (ret < 0 && ret != -ENOIOCTLCMD) + return ret; + + if (mf.code != xlate->code) + return -EINVAL; + + pix->width = mf.width; + pix->height = mf.height; + pix->field = mf.field; + pix->colorspace = mf.colorspace; + icd->current_fmt = xlate; + + return 0; +} + +static int mx2_camera_try_fmt(struct soc_camera_device *icd, + struct v4l2_format *f) +{ + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + struct mx2_camera_dev *pcdev = ici->priv; + struct v4l2_subdev *sd = soc_camera_to_subdev(icd); + const struct soc_camera_format_xlate *xlate; + struct v4l2_pix_format *pix = &f->fmt.pix; + struct v4l2_mbus_framefmt mf; + __u32 pixfmt = pix->pixelformat; + unsigned int width_limit; + int ret; + + xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); + if (pixfmt && !xlate) { + dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt); + return -EINVAL; + } + + /* FIXME: implement MX27 limits */ + + /* eMMA can only do RGB565 */ + if (mx27_camera_emma(pcdev) && pixfmt != V4L2_PIX_FMT_RGB565) + return -EINVAL; + + /* limit to MX25 hardware capabilities */ + if (cpu_is_mx25()) { + if (xlate->host_fmt->bits_per_sample <= 8) + width_limit = 0xffff * 4; + else + width_limit = 0xffff * 2; + /* CSIIMAG_PARA limit */ + if (pix->width > width_limit) + pix->width = width_limit; + if (pix->height > 0xffff) + pix->height = 0xffff; + + pix->bytesperline = soc_mbus_bytes_per_line(pix->width, + xlate->host_fmt); + if (pix->bytesperline < 0) + return pix->bytesperline; + pix->sizeimage = pix->height * pix->bytesperline; + if (pix->sizeimage > (4 * 0x3ffff)) { /* CSIRXCNT limit */ + dev_warn(icd->dev.parent, + "Image size (%u) above limit\n", + pix->sizeimage); + return -EINVAL; + } + } + + /* limit to sensor capabilities */ + mf.width = pix->width; + mf.height = pix->height; + mf.field = pix->field; + mf.colorspace = pix->colorspace; + mf.code = xlate->code; + + ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf); + if (ret < 0) + return ret; + + if (mf.field == V4L2_FIELD_ANY) + mf.field = V4L2_FIELD_NONE; + if (mf.field != V4L2_FIELD_NONE) { + dev_err(icd->dev.parent, "Field type %d unsupported.\n", + mf.field); + return -EINVAL; + } + + pix->width = mf.width; + pix->height = mf.height; + pix->field = mf.field; + pix->colorspace = mf.colorspace; + + return 0; +} + +static int mx2_camera_querycap(struct soc_camera_host *ici, + struct v4l2_capability *cap) +{ + /* cap->name is set by the friendly caller:-> */ + strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card)); + cap->version = MX2_CAM_VERSION_CODE; + cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; + + return 0; +} + +static int mx2_camera_reqbufs(struct soc_camera_file *icf, + struct v4l2_requestbuffers *p) +{ + int i; + + for (i = 0; i < p->count; i++) { + struct mx2_buffer *buf = container_of(icf->vb_vidq.bufs[i], + struct mx2_buffer, vb); + INIT_LIST_HEAD(&buf->vb.queue); + } + + return 0; +} + +#ifdef CONFIG_MACH_MX27 +static void mx27_camera_frame_done(struct mx2_camera_dev *pcdev, int state) +{ + struct videobuf_buffer *vb; + struct mx2_buffer *buf; + unsigned long flags; + int ret; + + spin_lock_irqsave(&pcdev->lock, flags); + + if (!pcdev->active) { + dev_err(pcdev->dev, "%s called with no active buffer!\n", + __func__); + goto out; + } + + vb = &pcdev->active->vb; + buf = container_of(vb, struct mx2_buffer, vb); + WARN_ON(list_empty(&vb->queue)); + dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, + vb, vb->baddr, vb->bsize); + + /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ + list_del_init(&vb->queue); + vb->state = state; + do_gettimeofday(&vb->ts); + vb->field_count++; + + wake_up(&vb->done); + + if (list_empty(&pcdev->capture)) { + pcdev->active = NULL; + goto out; + } + + pcdev->active = list_entry(pcdev->capture.next, + struct mx2_buffer, vb.queue); + + vb = &pcdev->active->vb; + vb->state = VIDEOBUF_ACTIVE; + + ret = imx_dma_setup_single(pcdev->dma, videobuf_to_dma_contig(vb), + vb->size, (u32)pcdev->base_dma + 0x10, DMA_MODE_READ); + + if (ret) { + vb->state = VIDEOBUF_ERROR; + pcdev->active = NULL; + wake_up(&vb->done); + } + +out: + spin_unlock_irqrestore(&pcdev->lock, flags); +} + +static void mx27_camera_dma_err_callback(int channel, void *data, int err) +{ + struct mx2_camera_dev *pcdev = data; + + mx27_camera_frame_done(pcdev, VIDEOBUF_ERROR); +} + +static void mx27_camera_dma_callback(int channel, void *data) +{ + struct mx2_camera_dev *pcdev = data; + + mx27_camera_frame_done(pcdev, VIDEOBUF_DONE); +} + +#define DMA_REQ_CSI_RX 31 /* FIXME: Add this to a resource */ + +static int __devinit mx27_camera_dma_init(struct platform_device *pdev, + struct mx2_camera_dev *pcdev) +{ + int err; + + pcdev->dma = imx_dma_request_by_prio("CSI RX DMA", DMA_PRIO_HIGH); + if (pcdev->dma < 0) { + dev_err(&pdev->dev, "%s failed to request DMA channel\n", + __func__); + return pcdev->dma; + } + + err = imx_dma_setup_handlers(pcdev->dma, mx27_camera_dma_callback, + mx27_camera_dma_err_callback, pcdev); + if (err) { + dev_err(&pdev->dev, "%s failed to set DMA callback\n", + __func__); + goto err_out; + } + + err = imx_dma_config_channel(pcdev->dma, + IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO, + IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR, + DMA_REQ_CSI_RX, 1); + if (err) { + dev_err(&pdev->dev, "%s failed to config DMA channel\n", + __func__); + goto err_out; + } + + imx_dma_config_burstlen(pcdev->dma, 64); + + return 0; + +err_out: + imx_dma_free(pcdev->dma); + + return err; +} +#endif /* CONFIG_MACH_MX27 */ + +static unsigned int mx2_camera_poll(struct file *file, poll_table *pt) +{ + struct soc_camera_file *icf = file->private_data; + + return videobuf_poll_stream(file, &icf->vb_vidq, pt); +} + +static struct soc_camera_host_ops mx2_soc_camera_host_ops = { + .owner = THIS_MODULE, + .add = mx2_camera_add_device, + .remove = mx2_camera_remove_device, + .set_fmt = mx2_camera_set_fmt, + .set_crop = mx2_camera_set_crop, + .try_fmt = mx2_camera_try_fmt, + .init_videobuf = mx2_camera_init_videobuf, + .reqbufs = mx2_camera_reqbufs, + .poll = mx2_camera_poll, + .querycap = mx2_camera_querycap, + .set_bus_param = mx2_camera_set_bus_param, +}; + +static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev, + int bufnum, int state) +{ + struct mx2_buffer *buf; + struct videobuf_buffer *vb; + unsigned long phys; + + if (!list_empty(&pcdev->active_bufs)) { + buf = list_entry(pcdev->active_bufs.next, + struct mx2_buffer, vb.queue); + + BUG_ON(buf->bufnum != bufnum); + + vb = &buf->vb; +#ifdef DEBUG + phys = videobuf_to_dma_contig(vb); + if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum) + != phys) { + dev_err(pcdev->dev, "%p != %p\n", phys, + readl(pcdev->base_emma + + PRP_DEST_RGB1_PTR + + 4 * bufnum)); + } +#endif + dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb, + vb->baddr, vb->bsize); + + list_del(&vb->queue); + vb->state = state; + do_gettimeofday(&vb->ts); + vb->field_count++; + + wake_up(&vb->done); + } + + if (list_empty(&pcdev->capture)) { + writel(pcdev->discard_buffer_dma, pcdev->base_emma + + PRP_DEST_RGB1_PTR + 4 * bufnum); + return; + } + + buf = list_entry(pcdev->capture.next, + struct mx2_buffer, vb.queue); + + buf->bufnum = bufnum; + + list_move_tail(pcdev->capture.next, &pcdev->active_bufs); + + vb = &buf->vb; + vb->state = VIDEOBUF_ACTIVE; + + phys = videobuf_to_dma_contig(vb); + writel(phys, pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum); +} + +static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data) +{ + struct mx2_camera_dev *pcdev = data; + unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS); + struct mx2_buffer *buf; + + if (status & (1 << 7)) { /* overflow */ + u32 cntl; + /* + * We only disable channel 1 here since this is the only + * enabled channel + * + * FIXME: the correct DMA overflow handling should be resetting + * the buffer, returning an error frame, and continuing with + * the next one. + */ + cntl = readl(pcdev->base_emma + PRP_CNTL); + writel(cntl & ~PRP_CNTL_CH1EN, pcdev->base_emma + PRP_CNTL); + writel(cntl, pcdev->base_emma + PRP_CNTL); + } + if ((status & (3 << 5)) == (3 << 5) + && !list_empty(&pcdev->active_bufs)) { + /* + * Both buffers have triggered, process the one we're expecting + * to first + */ + buf = list_entry(pcdev->active_bufs.next, + struct mx2_buffer, vb.queue); + mx27_camera_frame_done_emma(pcdev, buf->bufnum, VIDEOBUF_DONE); + status &= ~(1 << (6 - buf->bufnum)); /* mark processed */ + } + if (status & (1 << 6)) + mx27_camera_frame_done_emma(pcdev, 0, VIDEOBUF_DONE); + if (status & (1 << 5)) + mx27_camera_frame_done_emma(pcdev, 1, VIDEOBUF_DONE); + + writel(status, pcdev->base_emma + PRP_INTRSTATUS); + + return IRQ_HANDLED; +} + +static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev) +{ + struct resource *res_emma = pcdev->res_emma; + int err = 0; + + if (!request_mem_region(res_emma->start, resource_size(res_emma), + MX2_CAM_DRV_NAME)) { + err = -EBUSY; + goto out; + } + + pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma)); + if (!pcdev->base_emma) { + err = -ENOMEM; + goto exit_release; + } + + err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0, + MX2_CAM_DRV_NAME, pcdev); + if (err) { + dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n"); + goto exit_iounmap; + } + + pcdev->clk_emma = clk_get(NULL, "emma"); + if (IS_ERR(pcdev->clk_emma)) { + err = PTR_ERR(pcdev->clk_emma); + goto exit_free_irq; + } + + clk_enable(pcdev->clk_emma); + + err = mx27_camera_emma_prp_reset(pcdev); + if (err) + goto exit_clk_emma_put; + + return err; + +exit_clk_emma_put: + clk_disable(pcdev->clk_emma); + clk_put(pcdev->clk_emma); +exit_free_irq: + free_irq(pcdev->irq_emma, pcdev); +exit_iounmap: + iounmap(pcdev->base_emma); +exit_release: + release_mem_region(res_emma->start, resource_size(res_emma)); +out: + return err; +} + +static int __devinit mx2_camera_probe(struct platform_device *pdev) +{ + struct mx2_camera_dev *pcdev; + struct resource *res_csi, *res_emma; + void __iomem *base_csi; + int irq_csi, irq_emma; + irq_handler_t mx2_cam_irq_handler = cpu_is_mx25() ? mx25_camera_irq + : mx27_camera_irq; + int err = 0; + + dev_dbg(&pdev->dev, "initialising\n"); + + res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irq_csi = platform_get_irq(pdev, 0); + if (res_csi == NULL || irq_csi < 0) { + dev_err(&pdev->dev, "Missing platform resources data\n"); + err = -ENODEV; + goto exit; + } + + pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); + if (!pcdev) { + dev_err(&pdev->dev, "Could not allocate pcdev\n"); + err = -ENOMEM; + goto exit; + } + + pcdev->clk_csi = clk_get(&pdev->dev, NULL); + if (IS_ERR(pcdev->clk_csi)) { + err = PTR_ERR(pcdev->clk_csi); + goto exit_kfree; + } + + dev_dbg(&pdev->dev, "Camera clock frequency: %ld\n", + clk_get_rate(pcdev->clk_csi)); + + /* Initialize DMA */ +#ifdef CONFIG_MACH_MX27 + if (cpu_is_mx27()) { + err = mx27_camera_dma_init(pdev, pcdev); + if (err) + goto exit_clk_put; + } +#endif /* CONFIG_MACH_MX27 */ + + pcdev->res_csi = res_csi; + pcdev->pdata = pdev->dev.platform_data; + if (pcdev->pdata) { + long rate; + + pcdev->platform_flags = pcdev->pdata->flags; + + rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2); + if (rate <= 0) { + err = -ENODEV; + goto exit_dma_free; + } + err = clk_set_rate(pcdev->clk_csi, rate); + if (err < 0) + goto exit_dma_free; + } + + INIT_LIST_HEAD(&pcdev->capture); + INIT_LIST_HEAD(&pcdev->active_bufs); + spin_lock_init(&pcdev->lock); + + /* + * Request the regions. + */ + if (!request_mem_region(res_csi->start, resource_size(res_csi), + MX2_CAM_DRV_NAME)) { + err = -EBUSY; + goto exit_dma_free; + } + + base_csi = ioremap(res_csi->start, resource_size(res_csi)); + if (!base_csi) { + err = -ENOMEM; + goto exit_release; + } + pcdev->irq_csi = irq_csi; + pcdev->base_csi = base_csi; + pcdev->base_dma = res_csi->start; + pcdev->dev = &pdev->dev; + + err = request_irq(pcdev->irq_csi, mx2_cam_irq_handler, 0, + MX2_CAM_DRV_NAME, pcdev); + if (err) { + dev_err(pcdev->dev, "Camera interrupt register failed \n"); + goto exit_iounmap; + } + + if (cpu_is_mx27()) { + /* EMMA support */ + res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1); + irq_emma = platform_get_irq(pdev, 1); + + if (res_emma && irq_emma >= 0) { + dev_info(&pdev->dev, "Using EMMA\n"); + pcdev->use_emma = 1; + pcdev->res_emma = res_emma; + pcdev->irq_emma = irq_emma; + if (mx27_camera_emma_init(pcdev)) + goto exit_free_irq; + } + } + + pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME, + pcdev->soc_host.ops = &mx2_soc_camera_host_ops, + pcdev->soc_host.priv = pcdev; + pcdev->soc_host.v4l2_dev.dev = &pdev->dev; + pcdev->soc_host.nr = pdev->id; + err = soc_camera_host_register(&pcdev->soc_host); + if (err) + goto exit_free_emma; + + return 0; + +exit_free_emma: + if (mx27_camera_emma(pcdev)) { + free_irq(pcdev->irq_emma, pcdev); + clk_disable(pcdev->clk_emma); + clk_put(pcdev->clk_emma); + iounmap(pcdev->base_emma); + release_mem_region(res_emma->start, resource_size(res_emma)); + } +exit_free_irq: + free_irq(pcdev->irq_csi, pcdev); +exit_iounmap: + iounmap(base_csi); +exit_release: + release_mem_region(res_csi->start, resource_size(res_csi)); +exit_dma_free: +#ifdef CONFIG_MACH_MX27 + if (cpu_is_mx27()) + imx_dma_free(pcdev->dma); +exit_clk_put: + clk_put(pcdev->clk_csi); +#endif /* CONFIG_MACH_MX27 */ +exit_kfree: + kfree(pcdev); +exit: + return err; +} + +static int __devexit mx2_camera_remove(struct platform_device *pdev) +{ + struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); + struct mx2_camera_dev *pcdev = container_of(soc_host, + struct mx2_camera_dev, soc_host); + struct resource *res; + + clk_put(pcdev->clk_csi); +#ifdef CONFIG_MACH_MX27 + if (cpu_is_mx27()) + imx_dma_free(pcdev->dma); +#endif /* CONFIG_MACH_MX27 */ + free_irq(pcdev->irq_csi, pcdev); + if (mx27_camera_emma(pcdev)) + free_irq(pcdev->irq_emma, pcdev); + + soc_camera_host_unregister(&pcdev->soc_host); + + iounmap(pcdev->base_csi); + + if (mx27_camera_emma(pcdev)) { + clk_disable(pcdev->clk_emma); + clk_put(pcdev->clk_emma); + iounmap(pcdev->base_emma); + res = pcdev->res_emma; + release_mem_region(res->start, resource_size(res)); + } + + res = pcdev->res_csi; + release_mem_region(res->start, resource_size(res)); + + kfree(pcdev); + + dev_info(&pdev->dev, "MX2 Camera driver unloaded\n"); + + return 0; +} + +static struct platform_driver mx2_camera_driver = { + .driver = { + .name = MX2_CAM_DRV_NAME, + }, + .remove = __devexit_p(mx2_camera_remove), +}; + + +static int __init mx2_camera_init(void) +{ + return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe); +} + +static void __exit mx2_camera_exit(void) +{ + return platform_driver_unregister(&mx2_camera_driver); +} + +module_init(mx2_camera_init); +module_exit(mx2_camera_exit); + +MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver"); +MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c index d9d4a72e0ec..350f78e8624 100644 --- a/drivers/mmc/host/mxcmmc.c +++ b/drivers/mmc/host/mxcmmc.c @@ -119,6 +119,7 @@ struct mxcmci_host { int detect_irq; int dma; int do_dma; + int default_irq_mask; int use_sdio; unsigned int power_mode; struct imxmmc_platform_data *pdata; @@ -228,7 +229,7 @@ static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data) static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd, unsigned int cmdat) { - u32 int_cntr; + u32 int_cntr = host->default_irq_mask; unsigned long flags; WARN_ON(host->cmd != NULL); @@ -275,7 +276,7 @@ static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd, static void mxcmci_finish_request(struct mxcmci_host *host, struct mmc_request *req) { - u32 int_cntr = 0; + u32 int_cntr = host->default_irq_mask; unsigned long flags; spin_lock_irqsave(&host->lock, flags); @@ -585,6 +586,9 @@ static irqreturn_t mxcmci_irq(int irq, void *devid) (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE))) mxcmci_data_done(host, stat); #endif + if (host->default_irq_mask && + (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL))) + mmc_detect_change(host->mmc, msecs_to_jiffies(200)); return IRQ_HANDLED; } @@ -809,6 +813,12 @@ static int mxcmci_probe(struct platform_device *pdev) else mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; + if (host->pdata && host->pdata->dat3_card_detect) + host->default_irq_mask = + INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN; + else + host->default_irq_mask = 0; + host->res = r; host->irq = irq; @@ -835,7 +845,7 @@ static int mxcmci_probe(struct platform_device *pdev) /* recommended in data sheet */ writew(0x2db4, host->base + MMC_REG_READ_TO); - writel(0, host->base + MMC_REG_INT_CNTR); + writel(host->default_irq_mask, host->base + MMC_REG_INT_CNTR); #ifdef HAS_DMA host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW); @@ -926,43 +936,47 @@ static int mxcmci_remove(struct platform_device *pdev) } #ifdef CONFIG_PM -static int mxcmci_suspend(struct platform_device *dev, pm_message_t state) +static int mxcmci_suspend(struct device *dev) { - struct mmc_host *mmc = platform_get_drvdata(dev); + struct mmc_host *mmc = dev_get_drvdata(dev); + struct mxcmci_host *host = mmc_priv(mmc); int ret = 0; if (mmc) ret = mmc_suspend_host(mmc); + clk_disable(host->clk); return ret; } -static int mxcmci_resume(struct platform_device *dev) +static int mxcmci_resume(struct device *dev) { - struct mmc_host *mmc = platform_get_drvdata(dev); - struct mxcmci_host *host; + struct mmc_host *mmc = dev_get_drvdata(dev); + struct mxcmci_host *host = mmc_priv(mmc); int ret = 0; - if (mmc) { - host = mmc_priv(mmc); + clk_enable(host->clk); + if (mmc) ret = mmc_resume_host(mmc); - } return ret; } -#else -#define mxcmci_suspend NULL -#define mxcmci_resume NULL -#endif /* CONFIG_PM */ + +static const struct dev_pm_ops mxcmci_pm_ops = { + .suspend = mxcmci_suspend, + .resume = mxcmci_resume, +}; +#endif static struct platform_driver mxcmci_driver = { .probe = mxcmci_probe, .remove = mxcmci_remove, - .suspend = mxcmci_suspend, - .resume = mxcmci_resume, .driver = { .name = DRIVER_NAME, .owner = THIS_MODULE, +#ifdef CONFIG_PM + .pm = &mxcmci_pm_ops, +#endif } }; diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 82e94389824..0d76b169482 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -623,8 +623,7 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command, else host->buf_start = column + mtd->writesize; - if (mtd->writesize > 512) - command = NAND_CMD_READ0; /* only READ0 is valid */ + command = NAND_CMD_READ0; /* only READ0 is valid */ send_cmd(host, command, false); mxc_do_addr_cycle(mtd, column, page_addr); @@ -639,31 +638,11 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command, break; case NAND_CMD_SEQIN: - if (column >= mtd->writesize) { - /* - * FIXME: before send SEQIN command for write OOB, - * We must read one page out. - * For K9F1GXX has no READ1 command to set current HW - * pointer to spare area, we must write the whole page - * including OOB together. - */ - if (mtd->writesize > 512) - /* call ourself to read a page */ - mxc_nand_command(mtd, NAND_CMD_READ0, 0, - page_addr); - - host->buf_start = column; - - /* Set program pointer to spare region */ - if (mtd->writesize == 512) - send_cmd(host, NAND_CMD_READOOB, false); - } else { - host->buf_start = column; + if (column >= mtd->writesize) + /* call ourself to read a page */ + mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr); - /* Set program pointer to page start */ - if (mtd->writesize == 512) - send_cmd(host, NAND_CMD_READ0, false); - } + host->buf_start = column; send_cmd(host, command, false); mxc_do_addr_cycle(mtd, column, page_addr); @@ -853,6 +832,8 @@ static int __init mxcnd_probe(struct platform_device *pdev) parse_mtd_partitions(mtd, part_probes, &host->parts, 0); if (nr_parts > 0) add_mtd_partitions(mtd, host->parts, nr_parts); + else if (pdata->parts) + add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts); else #endif { diff --git a/drivers/usb/gadget/fsl_mxc_udc.c b/drivers/usb/gadget/fsl_mxc_udc.c index d0b8bde59e5..eafa6d2c5ed 100644 --- a/drivers/usb/gadget/fsl_mxc_udc.c +++ b/drivers/usb/gadget/fsl_mxc_udc.c @@ -30,7 +30,7 @@ int fsl_udc_clk_init(struct platform_device *pdev) pdata = pdev->dev.platform_data; - if (!cpu_is_mx35()) { + if (!cpu_is_mx35() && !cpu_is_mx25()) { mxc_ahb_clk = clk_get(&pdev->dev, "usb_ahb"); if (IS_ERR(mxc_ahb_clk)) return PTR_ERR(mxc_ahb_clk); diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index bd4027745aa..a8ad8ac120a 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -182,7 +182,7 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev) } clk_enable(priv->usbclk); - if (!cpu_is_mx35()) { + if (!cpu_is_mx35() && !cpu_is_mx25()) { priv->ahbclk = clk_get(dev, "usb_ahb"); if (IS_ERR(priv->ahbclk)) { ret = PTR_ERR(priv->ahbclk); diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c index b4b6deceed1..43f0639b1c1 100644 --- a/drivers/video/imxfb.c +++ b/drivers/video/imxfb.c @@ -175,6 +175,7 @@ struct imxfb_info { struct imx_fb_videomode *mode; int num_modes; + struct backlight_device *bl; void (*lcd_power)(int); void (*backlight_power)(int); @@ -449,6 +450,73 @@ static int imxfb_set_par(struct fb_info *info) return 0; } + + +static int imxfb_bl_get_brightness(struct backlight_device *bl) +{ + struct imxfb_info *fbi = bl_get_data(bl); + + return readl(fbi->regs + LCDC_PWMR) & 0xFF; +} + +static int imxfb_bl_update_status(struct backlight_device *bl) +{ + struct imxfb_info *fbi = bl_get_data(bl); + int brightness = bl->props.brightness; + + if (bl->props.power != FB_BLANK_UNBLANK) + brightness = 0; + if (bl->props.fb_blank != FB_BLANK_UNBLANK) + brightness = 0; + + fbi->pwmr = (fbi->pwmr & ~0xFF) | brightness; + + if (bl->props.fb_blank != FB_BLANK_UNBLANK) + clk_enable(fbi->clk); + writel(fbi->pwmr, fbi->regs + LCDC_PWMR); + if (bl->props.fb_blank != FB_BLANK_UNBLANK) + clk_disable(fbi->clk); + + return 0; +} + +static const struct backlight_ops imxfb_lcdc_bl_ops = { + .update_status = imxfb_bl_update_status, + .get_brightness = imxfb_bl_get_brightness, +}; + +static void imxfb_init_backlight(struct imxfb_info *fbi) +{ + struct backlight_properties props; + struct backlight_device *bl; + + if (fbi->bl) + return; + + memset(&props, 0, sizeof(struct backlight_properties)); + props.max_brightness = 0xff; + writel(fbi->pwmr, fbi->regs + LCDC_PWMR); + + bl = backlight_device_register("imxfb-bl", &fbi->pdev->dev, fbi, + &imxfb_lcdc_bl_ops, &props); + if (IS_ERR(bl)) { + dev_err(&fbi->pdev->dev, "error %ld on backlight register\n", + PTR_ERR(bl)); + return; + } + + fbi->bl = bl; + bl->props.power = FB_BLANK_UNBLANK; + bl->props.fb_blank = FB_BLANK_UNBLANK; + bl->props.brightness = imxfb_bl_get_brightness(bl); +} + +static void imxfb_exit_backlight(struct imxfb_info *fbi) +{ + if (fbi->bl) + backlight_device_unregister(fbi->bl); +} + static void imxfb_enable_controller(struct imxfb_info *fbi) { pr_debug("Enabling LCD controller\n"); @@ -579,7 +647,6 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf fbi->regs + LCDC_SIZE); writel(fbi->pcr, fbi->regs + LCDC_PCR); - writel(fbi->pwmr, fbi->regs + LCDC_PWMR); writel(fbi->lscr1, fbi->regs + LCDC_LSCR1); writel(fbi->dmacr, fbi->regs + LCDC_DMACR); @@ -779,6 +846,8 @@ static int __init imxfb_probe(struct platform_device *pdev) } imxfb_enable_controller(fbi); + fbi->pdev = pdev; + imxfb_init_backlight(fbi); return 0; @@ -816,6 +885,7 @@ static int __devexit imxfb_remove(struct platform_device *pdev) imxfb_disable_controller(fbi); + imxfb_exit_backlight(fbi); unregister_framebuffer(info); pdata = pdev->dev.platform_data; |