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authorKyungmin Park <kyungmin.park@samsung.com>2010-09-27 16:25:17 +0900
committerDavid Woodhouse <David.Woodhouse@intel.com>2010-10-25 00:50:09 +0100
commitebe8a642f50a0020bed317afcde1f9d2a9da429b (patch)
tree0bfc44174459b60ae434f35157b597fe3eced428
parent12a40a57f762f569f58a393437d8c13864db390a (diff)
mtd: OneNAND: S5PC110: Add timeout to prevent the endless loop
There's no case timeout but add it for some H/W problem or wrong codes implementation Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
-rw-r--r--drivers/mtd/onenand/samsung.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/mtd/onenand/samsung.c b/drivers/mtd/onenand/samsung.c
index 7913a921b08..b80128036a2 100644
--- a/drivers/mtd/onenand/samsung.c
+++ b/drivers/mtd/onenand/samsung.c
@@ -535,6 +535,7 @@ static int s5pc110_dma_ops(void *dst, void *src, size_t count, int direction)
{
void __iomem *base = onenand->dma_addr;
int status;
+ unsigned long timeout;
writel(src, base + S5PC110_DMA_SRC_ADDR);
writel(dst, base + S5PC110_DMA_DST_ADDR);
@@ -552,6 +553,13 @@ static int s5pc110_dma_ops(void *dst, void *src, size_t count, int direction)
writel(S5PC110_DMA_TRANS_CMD_TR, base + S5PC110_DMA_TRANS_CMD);
+ /*
+ * There's no exact timeout values at Spec.
+ * In real case it takes under 1 msec.
+ * So 20 msecs are enough.
+ */
+ timeout = jiffies + msecs_to_jiffies(20);
+
do {
status = readl(base + S5PC110_DMA_TRANS_STATUS);
if (status & S5PC110_DMA_TRANS_STATUS_TE) {
@@ -559,7 +567,8 @@ static int s5pc110_dma_ops(void *dst, void *src, size_t count, int direction)
base + S5PC110_DMA_TRANS_CMD);
return -EIO;
}
- } while (!(status & S5PC110_DMA_TRANS_STATUS_TD));
+ } while (!(status & S5PC110_DMA_TRANS_STATUS_TD) &&
+ time_before(jiffies, timeout));
writel(S5PC110_DMA_TRANS_CMD_TDC, base + S5PC110_DMA_TRANS_CMD);