diff options
| author | Giuseppe CAVALLARO <peppe.cavallaro@st.com> | 2011-10-10 21:37:56 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2011-10-18 23:50:02 -0400 |
| commit | a4886d522e18e5d4a63b95a5ead72f6105e3ef98 (patch) | |
| tree | 0114dbc86ccdd7a4ca1419e121a8f06a9fe4a895 | |
| parent | 2425717b27eb92b175335ca4ff0bb218cbe0cb64 (diff) | |
net/phy: extra delay only for RGMII interfaces for IC+ IP 1001
The extra delay of 2ns to adjust RX clock phase is actually needed
in RGMII mode. Tested on the HDK7108 (STx7108c2).
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/phy/icplus.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c index d66bd8d1259..c81f136ae67 100644 --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c @@ -128,12 +128,15 @@ static int ip1001_config_init(struct phy_device *phydev) if (c < 0) return c; - /* Additional delay (2ns) used to adjust RX clock phase - * at GMII/ RGMII interface */ - c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS); - c |= IP1001_PHASE_SEL_MASK; + if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { + /* Additional delay (2ns) used to adjust RX clock phase + * at RGMII interface */ + c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS); + c |= IP1001_PHASE_SEL_MASK; + c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c); + } - return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c); + return c; } static int ip101a_config_init(struct phy_device *phydev) |