diff options
| author | Jongpill Lee <boyko.lee@samsung.com> | 2010-08-18 22:13:49 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2010-08-27 18:06:54 +0900 |
| commit | 4d235f7934ab55329a5cb34d7e3949ba50b511d4 (patch) | |
| tree | 0897d078f8807c547db9808ad2830efd05ca635e | |
| parent | c598c47d85cbc0ac04ba808a696d774baa7a0a34 (diff) | |
ARM: S5PV310: Fix on PLL setting for S5PV310
This patch fixes on PLL setting for S5PV310/S5PC210.
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| -rw-r--r-- | arch/arm/mach-s5pv310/clock.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index 77f2b4d85e6..1659eb1e7b0 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -470,11 +470,11 @@ void __init_or_cpufreq s5pv310_setup_clocks(void) apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508); mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508); epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0), - __raw_readl(S5P_EPLL_CON1), pll_4500); + __raw_readl(S5P_EPLL_CON1), pll_4600); vpllsrc = clk_get_rate(&clk_vpllsrc.clk); vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), - __raw_readl(S5P_VPLL_CON1), pll_4502); + __raw_readl(S5P_VPLL_CON1), pll_4650); clk_fout_apll.rate = apll; clk_fout_mpll.rate = mpll; |