diff options
| author | Tuomas Tynkkynen <ttynkkynen@nvidia.com> | 2013-08-28 18:18:47 +0300 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2013-08-28 19:08:09 -0700 |
| commit | 89ac8567b97fea558238c4bb73637471f9197813 (patch) | |
| tree | aae20760c9d0163f2ae08484dd6b544d946a7efa | |
| parent | 5b0dde99e8a9971030b36096ee1dc85a1a12ff57 (diff) | |
clk: tegra30: Don't wait for PLL_U lock bit
The lock bit on PLL_U does not seem to be working correctly and
sometimes never gets set when waiting for the PLL to come up.
Remove the TEGRA_PLL_USE_LOCK flag to use a constant delay.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
| -rw-r--r-- | drivers/clk/tegra/clk-tegra30.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index b09ebf64cdc..dbe7c8003c5 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -971,7 +971,7 @@ static void __init tegra30_pll_init(void) /* PLLU */ clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0, 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | - TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK, + TEGRA_PLL_SET_LFCON, pll_u_freq_table, NULL); clk_register_clkdev(clk, "pll_u", NULL); |