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authorYouquan Song <youquan.song@intel.com>2012-12-18 12:20:23 -0500
committerIngo Molnar <mingo@kernel.org>2013-01-24 16:14:04 +0100
commit923d8697e24847000490c187de1aeaca622611a3 (patch)
tree762e0eae44554d2cc2b7c5c760d46c517a3d30b1
parent9faec5be3a27f95ee359b42c6c81b3173eb13958 (diff)
x86/perf: Add IvyBridge EP support
Running the perf utility on a Ivybridge EP server we encounter "not supported" events: <not supported> L1-dcache-loads <not supported> L1-dcache-load-misses <not supported> L1-dcache-stores <not supported> L1-dcache-store-misses <not supported> L1-dcache-prefetches <not supported> L1-dcache-prefetch-misses This patch adds support for this processor. Signed-off-by: Youquan Song <youquan.song@intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Youquan Song <youquan.song@linux.intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Link: http://lkml.kernel.org/r/1355851223-27705-1-git-send-email-youquan.song@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index cb313a56c21..4914e94ad6e 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2087,6 +2087,7 @@ __init int intel_pmu_init(void)
pr_cont("SandyBridge events, ");
break;
case 58: /* IvyBridge */
+ case 62: /* IvyBridge EP */
memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,