Blackfin arch: Fix PM building on BF52x: No ROTWE on BF52x, add USBWE

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>

2 files changed, 89 insertions, 98 deletions

diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
index fc69cf93f14..6ac2ed7026e 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@@ -151,7 +151,7 @@
 #define TIMER7_CONFIG		0xFFC00670	/* Timer 7 Configuration Register  			*/
 #define TIMER7_COUNTER		0xFFC00674	/* Timer 7 Counter Register        			*/
 #define TIMER7_PERIOD		0xFFC00678	/* Timer 7 Period Register         			*/
-#define TIMER7_WIDTH		0xFFC0067C	/* Timer 7 Width Register       			*/   
+#define TIMER7_WIDTH		0xFFC0067C	/* Timer 7 Width Register       			*/
 
 #define TIMER_ENABLE		0xFFC00680	/* Timer Enable Register					*/
 #define TIMER_DISABLE		0xFFC00684	/* Timer Disable Register					*/
@@ -634,18 +634,9 @@
 /* PLL_DIV Macros														*/
 #define SET_SSEL(x)		((x)&0xF)		/* Set SSEL = 0-15 --> SCLK = VCO/SSEL	*/
 
-/* VR_CTL Masks																	*/
-#define	FREQ			0x0003	/* Switching Oscillator Frequency For Regulator	*/
+/* VR_CTL Masks	*/
+#define	FREQ			0x3000	/* Switching Oscillator Frequency For Regulator	*/
 #define	HIBERNATE		0x0000	/* 		Powerdown/Bypass On-Board Regulation	*/
-#define	FREQ_333		0x0001	/* 		Switching Frequency Is 333 kHz			*/
-#define	FREQ_667		0x0002	/* 		Switching Frequency Is 667 kHz			*/
-#define	FREQ_1000		0x0003	/* 		Switching Frequency Is 1 MHz			*/
-
-#define GAIN			0x000C	/* Voltage Level Gain	*/
-#define	GAIN_5			0x0000	/* 		GAIN = 5		*/
-#define	GAIN_10			0x0004	/* 		GAIN = 10		*/
-#define	GAIN_20			0x0008	/* 		GAIN = 20		*/
-#define	GAIN_50			0x000C	/* 		GAIN = 50		*/
 
 #define	VLEV			0x00F0	/* Internal Voltage Level					*/
 #define	VLEV_085 		0x0060	/* 		VLEV = 0.85 V (-5% - +10% Accuracy)	*/
@@ -660,7 +651,7 @@
 #define	VLEV_130		0x00F0	/* 		VLEV = 1.30 V (-5% - +10% Accuracy)	*/
 
 #define	WAKE			0x0100	/* Enable RTC/Reset Wakeup From Hibernate	*/
-#define	CANWE			0x0200	/* Enable CAN Wakeup From Hibernate			*/
+#define	USBWE			0x0200	/* Enable USB Wakeup From Hibernate			*/
 #define	PHYWE			0x0400	/* Enable PHY Wakeup From Hibernate			*/
 #define	CLKBUFOE		0x4000	/* CLKIN Buffer Output Enable */
 #define	PHYCLKOE		CLKBUFOE	/* Alternative legacy name for the above */
@@ -697,16 +688,16 @@
 
 #define IRQ_ERROR1      0x00000002  /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
 #define IRQ_ERROR2      0x00000004  /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
-#define IRQ_RTC			0x00000008	/* Real Time Clock Interrupt 						*/ 
-#define IRQ_DMA0		0x00000010	/* DMA Channel 0 (PPI) Interrupt 					*/ 
-#define IRQ_DMA3		0x00000020	/* DMA Channel 3 (SPORT0 RX) Interrupt 				*/ 
+#define IRQ_RTC			0x00000008	/* Real Time Clock Interrupt 						*/
+#define IRQ_DMA0		0x00000010	/* DMA Channel 0 (PPI) Interrupt 					*/
+#define IRQ_DMA3		0x00000020	/* DMA Channel 3 (SPORT0 RX) Interrupt 				*/
 #define IRQ_DMA4		0x00000040	/* DMA Channel 4 (SPORT0 TX) Interrupt 				*/
 #define IRQ_DMA5		0x00000080	/* DMA Channel 5 (SPORT1 RX) Interrupt 				*/
 
 #define IRQ_DMA6		0x00000100	/* DMA Channel 6 (SPORT1 TX) Interrupt 		 		*/
 #define IRQ_TWI			0x00000200	/* TWI Interrupt									*/
 #define IRQ_DMA7		0x00000400	/* DMA Channel 7 (SPI) Interrupt 					*/
-#define IRQ_DMA8		0x00000800	/* DMA Channel 8 (UART0 RX) Interrupt 				*/ 
+#define IRQ_DMA8		0x00000800	/* DMA Channel 8 (UART0 RX) Interrupt 				*/
 #define IRQ_DMA9		0x00001000	/* DMA Channel 9 (UART0 TX) Interrupt 				*/
 #define IRQ_DMA10		0x00002000	/* DMA Channel 10 (UART1 RX) Interrupt 				*/
 #define IRQ_DMA11		0x00004000	/* DMA Channel 11 (UART1 TX) Interrupt 				*/
@@ -801,7 +792,7 @@
 #define WDEV_NONE 0x0006 /* no event on roll over */
 #define WDEN 0x0FF0 /* enable watchdog */
 #define WDDIS 0x0AD0 /* disable watchdog */
-#define WDRO 0x8000 /* watchdog rolled over latch */ 
+#define WDRO 0x8000 /* watchdog rolled over latch */
 
 /* depreciated WDOG_CTL Register Masks for legacy code */
 
@@ -882,7 +873,7 @@
 #define NINT		0x01		/* Pending Interrupt					*/
 #define IIR_TX_READY    0x02		/* UART_THR empty                               */
 #define IIR_RX_READY    0x04		/* Receive data ready                           */
-#define IIR_LINE_CHANGE 0x06		/* Receive line status    			*/ 
+#define IIR_LINE_CHANGE 0x06		/* Receive line status    			*/
 #define IIR_STATUS	0x06		/* Highest Priority Pending Interrupt	*/
 
 /* UARTx_GCTL Masks													*/
@@ -1638,12 +1629,12 @@
 
 /* entry addresses of the user-callable Boot ROM functions */
 
-#define _BOOTROM_RESET 0xEF000000 
-#define _BOOTROM_FINAL_INIT 0xEF000002 
+#define _BOOTROM_RESET 0xEF000000
+#define _BOOTROM_FINAL_INIT 0xEF000002
 #define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A 
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C 
+#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
+#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
+#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
 #define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
 #define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
 #define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
@@ -1771,71 +1762,71 @@
 /* Bit masks for CNT_CONFIG */
 
 #define                      CNTE  0x1        /* Counter Enable */
-#define                     nCNTE  0x0       
+#define                     nCNTE  0x0
 #define                      DEBE  0x2        /* Debounce Enable */
-#define                     nDEBE  0x0       
+#define                     nDEBE  0x0
 #define                    CDGINV  0x10       /* CDG Pin Polarity Invert */
-#define                   nCDGINV  0x0       
+#define                   nCDGINV  0x0
 #define                    CUDINV  0x20       /* CUD Pin Polarity Invert */
-#define                   nCUDINV  0x0       
+#define                   nCUDINV  0x0
 #define                    CZMINV  0x40       /* CZM Pin Polarity Invert */
-#define                   nCZMINV  0x0       
+#define                   nCZMINV  0x0
 #define                   CNTMODE  0x700      /* Counter Operating Mode */
 #define                      ZMZC  0x800      /* CZM Zeroes Counter Enable */
-#define                     nZMZC  0x0       
+#define                     nZMZC  0x0
 #define                   BNDMODE  0x3000     /* Boundary register Mode */
 #define                    INPDIS  0x8000     /* CUG and CDG Input Disable */
-#define                   nINPDIS  0x0       
+#define                   nINPDIS  0x0
 
 /* Bit masks for CNT_IMASK */
 
 #define                      ICIE  0x1        /* Illegal Gray/Binary Code Interrupt Enable */
-#define                     nICIE  0x0       
+#define                     nICIE  0x0
 #define                      UCIE  0x2        /* Up count Interrupt Enable */
-#define                     nUCIE  0x0       
+#define                     nUCIE  0x0
 #define                      DCIE  0x4        /* Down count Interrupt Enable */
-#define                     nDCIE  0x0       
+#define                     nDCIE  0x0
 #define                    MINCIE  0x8        /* Min Count Interrupt Enable */
-#define                   nMINCIE  0x0       
+#define                   nMINCIE  0x0
 #define                    MAXCIE  0x10       /* Max Count Interrupt Enable */
-#define                   nMAXCIE  0x0       
+#define                   nMAXCIE  0x0
 #define                   COV31IE  0x20       /* Bit 31 Overflow Interrupt Enable */
-#define                  nCOV31IE  0x0       
+#define                  nCOV31IE  0x0
 #define                   COV15IE  0x40       /* Bit 15 Overflow Interrupt Enable */
-#define                  nCOV15IE  0x0       
+#define                  nCOV15IE  0x0
 #define                   CZEROIE  0x80       /* Count to Zero Interrupt Enable */
-#define                  nCZEROIE  0x0       
+#define                  nCZEROIE  0x0
 #define                     CZMIE  0x100      /* CZM Pin Interrupt Enable */
-#define                    nCZMIE  0x0       
+#define                    nCZMIE  0x0
 #define                    CZMEIE  0x200      /* CZM Error Interrupt Enable */
-#define                   nCZMEIE  0x0       
+#define                   nCZMEIE  0x0
 #define                    CZMZIE  0x400      /* CZM Zeroes Counter Interrupt Enable */
-#define                   nCZMZIE  0x0       
+#define                   nCZMZIE  0x0
 
 /* Bit masks for CNT_STATUS */
 
 #define                      ICII  0x1        /* Illegal Gray/Binary Code Interrupt Identifier */
-#define                     nICII  0x0       
+#define                     nICII  0x0
 #define                      UCII  0x2        /* Up count Interrupt Identifier */
-#define                     nUCII  0x0       
+#define                     nUCII  0x0
 #define                      DCII  0x4        /* Down count Interrupt Identifier */
-#define                     nDCII  0x0       
+#define                     nDCII  0x0
 #define                    MINCII  0x8        /* Min Count Interrupt Identifier */
-#define                   nMINCII  0x0       
+#define                   nMINCII  0x0
 #define                    MAXCII  0x10       /* Max Count Interrupt Identifier */
-#define                   nMAXCII  0x0       
+#define                   nMAXCII  0x0
 #define                   COV31II  0x20       /* Bit 31 Overflow Interrupt Identifier */
-#define                  nCOV31II  0x0       
+#define                  nCOV31II  0x0
 #define                   COV15II  0x40       /* Bit 15 Overflow Interrupt Identifier */
-#define                  nCOV15II  0x0       
+#define                  nCOV15II  0x0
 #define                   CZEROII  0x80       /* Count to Zero Interrupt Identifier */
-#define                  nCZEROII  0x0       
+#define                  nCZEROII  0x0
 #define                     CZMII  0x100      /* CZM Pin Interrupt Identifier */
-#define                    nCZMII  0x0       
+#define                    nCZMII  0x0
 #define                    CZMEII  0x200      /* CZM Error Interrupt Identifier */
-#define                   nCZMEII  0x0       
+#define                   nCZMEII  0x0
 #define                    CZMZII  0x400      /* CZM Zeroes Counter Interrupt Identifier */
-#define                   nCZMZII  0x0       
+#define                   nCZMZII  0x0
 
 /* Bit masks for CNT_COMMAND */
 
@@ -1843,7 +1834,7 @@
 #define                    W1LMIN  0xf0       /* Load Min Register */
 #define                    W1LMAX  0xf00      /* Load Max Register */
 #define                  W1ZMONCE  0x1000     /* Enable CZM Clear Counter Once */
-#define                 nW1ZMONCE  0x0       
+#define                 nW1ZMONCE  0x0
 
 /* Bit masks for CNT_DEBOUNCE */
 
@@ -1853,15 +1844,15 @@
 
 #define                FUSE_FADDR  0x1ff      /* OTP/Fuse Address */
 #define                      FIEN  0x800      /* OTP/Fuse Interrupt Enable */
-#define                     nFIEN  0x0       
+#define                     nFIEN  0x0
 #define                  FTESTDEC  0x1000     /* OTP/Fuse Test Decoder */
-#define                 nFTESTDEC  0x0       
+#define                 nFTESTDEC  0x0
 #define                   FWRTEST  0x2000     /* OTP/Fuse Write Test */
-#define                  nFWRTEST  0x0       
+#define                  nFWRTEST  0x0
 #define                     FRDEN  0x4000     /* OTP/Fuse Read Enable */
-#define                    nFRDEN  0x0       
+#define                    nFRDEN  0x0
 #define                     FWREN  0x8000     /* OTP/Fuse Write Enable */
-#define                    nFWREN  0x0       
+#define                    nFWREN  0x0
 
 /* Bit masks for OTP_BEN */
 
@@ -1870,15 +1861,15 @@
 /* Bit masks for OTP_STATUS */
 
 #define                     FCOMP  0x1        /* OTP/Fuse Access Complete */
-#define                    nFCOMP  0x0       
+#define                    nFCOMP  0x0
 #define                    FERROR  0x2        /* OTP/Fuse Access Error */
-#define                   nFERROR  0x0       
+#define                   nFERROR  0x0
 #define                  MMRGLOAD  0x10       /* Memory Mapped Register Gasket Load */
-#define                 nMMRGLOAD  0x0       
+#define                 nMMRGLOAD  0x0
 #define                  MMRGLOCK  0x20       /* Memory Mapped Register Gasket Lock */
-#define                 nMMRGLOCK  0x0       
+#define                 nMMRGLOCK  0x0
 #define                    FPGMEN  0x40       /* OTP/Fuse Program Enable */
-#define                   nFPGMEN  0x0       
+#define                   nFPGMEN  0x0
 
 /* Bit masks for OTP_TIMING */
 
@@ -1892,42 +1883,42 @@
 /* Bit masks for SECURE_SYSSWT */
 
 #define                   EMUDABL  0x1        /* Emulation Disable. */
-#define                  nEMUDABL  0x0       
+#define                  nEMUDABL  0x0
 #define                   RSTDABL  0x2        /* Reset Disable */
-#define                  nRSTDABL  0x0       
+#define                  nRSTDABL  0x0
 #define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
 #define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
 #define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
 #define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
-#define                  nDMA0OVR  0x0       
+#define                  nDMA0OVR  0x0
 #define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
-#define                  nDMA1OVR  0x0       
+#define                  nDMA1OVR  0x0
 #define                    EMUOVR  0x4000     /* Emulation Override */
-#define                   nEMUOVR  0x0       
+#define                   nEMUOVR  0x0
 #define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
-#define                   nOTPSEN  0x0       
+#define                   nOTPSEN  0x0
 #define                    L2DABL  0x70000    /* L2 Memory Disable. */
 
 /* Bit masks for SECURE_CONTROL */
 
 #define                   SECURE0  0x1        /* SECURE 0 */
-#define                  nSECURE0  0x0       
+#define                  nSECURE0  0x0
 #define                   SECURE1  0x2        /* SECURE 1 */
-#define                  nSECURE1  0x0       
+#define                  nSECURE1  0x0
 #define                   SECURE2  0x4        /* SECURE 2 */
-#define                  nSECURE2  0x0       
+#define                  nSECURE2  0x0
 #define                   SECURE3  0x8        /* SECURE 3 */
-#define                  nSECURE3  0x0       
+#define                  nSECURE3  0x0
 
 /* Bit masks for SECURE_STATUS */
 
 #define                   SECMODE  0x3        /* Secured Mode Control State */
 #define                       NMI  0x4        /* Non Maskable Interrupt */
-#define                      nNMI  0x0       
+#define                      nNMI  0x0
 #define                   AFVALID  0x8        /* Authentication Firmware Valid */
-#define                  nAFVALID  0x0       
+#define                  nAFVALID  0x0
 #define                    AFEXIT  0x10       /* Authentication Firmware Exit */
-#define                   nAFEXIT  0x0       
+#define                   nAFEXIT  0x0
 #define                   SECSTAT  0xe0       /* Secure Status */
 
 /* Bit masks for NFC_CTL */
@@ -1935,60 +1926,60 @@
 #define                    WR_DLY  0xf        /* Write Strobe Delay */
 #define                    RD_DLY  0xf0       /* Read Strobe Delay */
 #define                    NWIDTH  0x100      /* NAND Data Width */
-#define                   nNWIDTH  0x0       
+#define                   nNWIDTH  0x0
 #define                   PG_SIZE  0x200      /* Page Size */
-#define                  nPG_SIZE  0x0       
+#define                  nPG_SIZE  0x0
 
 /* Bit masks for NFC_STAT */
 
 #define                     NBUSY  0x1        /* Not Busy */
-#define                    nNBUSY  0x0       
+#define                    nNBUSY  0x0
 #define                   WB_FULL  0x2        /* Write Buffer Full */
-#define                  nWB_FULL  0x0       
+#define                  nWB_FULL  0x0
 #define                PG_WR_STAT  0x4        /* Page Write Pending */
-#define               nPG_WR_STAT  0x0       
+#define               nPG_WR_STAT  0x0
 #define                PG_RD_STAT  0x8        /* Page Read Pending */
-#define               nPG_RD_STAT  0x0       
+#define               nPG_RD_STAT  0x0
 #define                  WB_EMPTY  0x10       /* Write Buffer Empty */
-#define                 nWB_EMPTY  0x0       
+#define                 nWB_EMPTY  0x0
 
 /* Bit masks for NFC_IRQSTAT */
 
 #define                  NBUSYIRQ  0x1        /* Not Busy IRQ */
-#define                 nNBUSYIRQ  0x0       
+#define                 nNBUSYIRQ  0x0
 #define                    WB_OVF  0x2        /* Write Buffer Overflow */
-#define                   nWB_OVF  0x0       
+#define                   nWB_OVF  0x0
 #define                   WB_EDGE  0x4        /* Write Buffer Edge Detect */
-#define                  nWB_EDGE  0x0       
+#define                  nWB_EDGE  0x0
 #define                    RD_RDY  0x8        /* Read Data Ready */
-#define                   nRD_RDY  0x0       
+#define                   nRD_RDY  0x0
 #define                   WR_DONE  0x10       /* Page Write Done */
-#define                  nWR_DONE  0x0       
+#define                  nWR_DONE  0x0
 
 /* Bit masks for NFC_IRQMASK */
 
 #define              MASK_BUSYIRQ  0x1        /* Mask Not Busy IRQ */
-#define             nMASK_BUSYIRQ  0x0       
+#define             nMASK_BUSYIRQ  0x0
 #define                MASK_WBOVF  0x2        /* Mask Write Buffer Overflow */
-#define               nMASK_WBOVF  0x0       
+#define               nMASK_WBOVF  0x0
 #define              MASK_WBEMPTY  0x4        /* Mask Write Buffer Empty */
-#define             nMASK_WBEMPTY  0x0       
+#define             nMASK_WBEMPTY  0x0
 #define                MASK_RDRDY  0x8        /* Mask Read Data Ready */
-#define               nMASK_RDRDY  0x0       
+#define               nMASK_RDRDY  0x0
 #define               MASK_WRDONE  0x10       /* Mask Write Done */
-#define              nMASK_WRDONE  0x0       
+#define              nMASK_WRDONE  0x0
 
 /* Bit masks for NFC_RST */
 
 #define                   ECC_RST  0x1        /* ECC (and NFC counters) Reset */
-#define                  nECC_RST  0x0       
+#define                  nECC_RST  0x0
 
 /* Bit masks for NFC_PGCTL */
 
 #define               PG_RD_START  0x1        /* Page Read Start */
-#define              nPG_RD_START  0x0       
+#define              nPG_RD_START  0x0
 #define               PG_WR_START  0x2        /* Page Write Start */
-#define              nPG_WR_START  0x0       
+#define              nPG_WR_START  0x0
 
 /* Bit masks for NFC_ECC0 */
 
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 6dac86995d1..5fa536727c6 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -216,7 +216,7 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 	wakeup |= KPADWE;
 	break;
 #endif
-#ifdef IRQ_CNT
+#ifdef CONFIG_BF54x
 	case IRQ_CNT:
 	wakeup |= ROTWE;
 	break;