diff options
| author | Jonghwan Choi <jhbird.choi@samsung.com> | 2011-08-23 16:27:17 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-09-15 13:59:58 +0900 |
| commit | 6861a197e2ed6dd05c0316ee2006730fbb6e7f9a (patch) | |
| tree | d9cf3ffaab715fa4e88bfe1ab8f589acfbfa4e24 | |
| parent | b6fd41e29dea9c6753b1843a77e50433e6123bcb (diff) | |
ARM: EXYNOS4: Fix wrong pll type for vpll
The PLL4650C is used for VPLL on EXYNOS4 so should be fixed.
Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
[kgene.kim@samsung.com: added message]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| -rw-r--r-- | arch/arm/mach-exynos4/clock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c index 1561b036a9b..79d6cd0c8e7 100644 --- a/arch/arm/mach-exynos4/clock.c +++ b/arch/arm/mach-exynos4/clock.c @@ -1160,7 +1160,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void) vpllsrc = clk_get_rate(&clk_vpllsrc.clk); vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), - __raw_readl(S5P_VPLL_CON1), pll_4650); + __raw_readl(S5P_VPLL_CON1), pll_4650c); clk_fout_apll.ops = &exynos4_fout_apll_ops; clk_fout_mpll.rate = mpll; |