diff options
| author | Tushar Behera <tushar.behera@linaro.org> | 2011-12-29 16:48:08 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2012-01-12 02:20:59 +0900 |
| commit | 815ed6fc0a4d82bb39ed43d230c4e516214987e7 (patch) | |
| tree | 43292f0d06dc5f1525b1da265e056408b9d35e01 | |
| parent | 6e11e0bd82ecacd13b839558a49f65ebc958e1bd (diff) | |
ARM: EXYNOS: Invert VCLK polarity for framebuffer on ORIGEN
Framebuffer driver needs to fetch the video data during the rising
edge of the VCLK. Otherwise, there are some glitches in the LCD
display.
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| -rw-r--r-- | arch/arm/mach-exynos/mach-origen.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c index 2b11e046d39..0679b8ad2d1 100644 --- a/arch/arm/mach-exynos/mach-origen.c +++ b/arch/arm/mach-exynos/mach-origen.c @@ -597,7 +597,8 @@ static struct s3c_fb_pd_win origen_fb_win0 = { static struct s3c_fb_platdata origen_lcd_pdata __initdata = { .win[0] = &origen_fb_win0, .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | + VIDCON1_INV_VCLK, .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, }; |