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authorIngo Molnar <mingo@elte.hu>2009-11-26 10:50:39 +0100
committerIngo Molnar <mingo@elte.hu>2009-11-26 10:50:42 +0100
commit16bc67edeb49b531940b2ba6c183780a1b5c472d (patch)
tree71b4bc48e47e54f2c0b3126d8f81d2f31b707ea8 /Documentation/ABI/testing/sysfs-devices-cache_disable
parentf6630114d9198aa959ac95c131334c020038f253 (diff)
parent047106adcc85e3023da210143a6ab8a55df9e0fc (diff)
Merge branch 'sched/urgent' into sched/core
Merge reason: Pick up fixes that did not make it into .32.0 Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@@ -1,18 +0,0 @@
-What: /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X
-Date: August 2008
-KernelVersion: 2.6.27
-Contact: mark.langsdorf@amd.com
-Description: These files exist in every cpu's cache index directories.
- There are currently 2 cache_disable_# files in each
- directory. Reading from these files on a supported
- processor will return that cache disable index value
- for that processor and node. Writing to one of these
- files will cause the specificed cache index to be disabled.
-
- Currently, only AMD Family 10h Processors support cache index
- disable, and only for their L3 caches. See the BIOS and
- Kernel Developer's Guide at
- http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116-Public-GH-BKDG_3.20_2-4-09.pdf
- for formatting information and other details on the
- cache index disable.
-Users: joachim.deguara@amd.com