diff options
| author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2008-08-08 16:21:02 -0400 |
|---|---|---|
| committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2008-08-08 16:21:02 -0400 |
| commit | e4ddcb0a6bf04d53ce77b4eb87bbbb32c4261d11 (patch) | |
| tree | d27d2fea50a384d97aa2d0cf5c8657c916f761d4 /Documentation/DMA-attributes.txt | |
| parent | f2afa7711f8585ffc088ba538b9a510e0d5dca12 (diff) | |
| parent | 6e86841d05f371b5b9b86ce76c02aaee83352298 (diff) | |
Merge commit 'v2.6.27-rc1' into for-linus
Diffstat (limited to 'Documentation/DMA-attributes.txt')
| -rw-r--r-- | Documentation/DMA-attributes.txt | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/Documentation/DMA-attributes.txt b/Documentation/DMA-attributes.txt index 6d772f84b47..b768cc0e402 100644 --- a/Documentation/DMA-attributes.txt +++ b/Documentation/DMA-attributes.txt @@ -22,3 +22,12 @@ ready and available in memory. The DMA of the "completion indication" could race with data DMA. Mapping the memory used for completion indications with DMA_ATTR_WRITE_BARRIER would prevent the race. +DMA_ATTR_WEAK_ORDERING +---------------------- + +DMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping +may be weakly ordered, that is that reads and writes may pass each other. + +Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING, +those that do not will simply ignore the attribute and exhibit default +behavior. |