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authorShinya Kuribayashi <shinya.kuribayashi@necel.com>2009-11-06 21:48:12 +0900
committerBen Dooks <ben-linux@fluff.org>2009-12-09 00:19:11 +0000
commit4cb6d1d6da471d795320cc4a933ce60f415dd1f6 (patch)
tree0ca9f5254f74590f8f3bd72064b327a77395e01c /Documentation/IPMI.txt
parent0774539948b23984f1c866135ba307fa2c441d0e (diff)
i2c-designware: Set Tx/Rx FIFO threshold levels
As a hardware feature, DW I2C core generates a STOP condition whenever the Tx FIFO becomes empty (strictly speaking, whenever the last byte in the Tx FIFO is sent out), even if we have more bytes to be written. In other words, we must never make "Tx FIFO underrun" happen during a transaction, except for the last byte. For the safety's sake, we'd make TX_EMPTY interrupt get triggered every time one byte is processed. The Rx FIFO threshold needs to be set as well. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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