diff options
| author | Roland Stigge <stigge@antcom.de> | 2012-04-22 12:01:19 +0200 |
|---|---|---|
| committer | Roland Stigge <stigge@antcom.de> | 2012-04-22 12:01:19 +0200 |
| commit | f5c422713308e492eddc44a12134f9f249ddfbdb (patch) | |
| tree | f5f3f115b40aada230e8d413429000a0a7741991 /Documentation/devicetree/bindings/arm | |
| parent | e04920d9efcb3517cabc61a55a3ce4bce51518bc (diff) | |
ARM: LPC32xx: Device tree support
This patch does the actual device tree switch for the LPC32xx SoC.
Signed-off-by: Roland Stigge <stigge@antcom.de>
Diffstat (limited to 'Documentation/devicetree/bindings/arm')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/lpc32xx-mic.txt | 38 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/arm/lpc32xx.txt | 8 |
2 files changed, 46 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/lpc32xx-mic.txt b/Documentation/devicetree/bindings/arm/lpc32xx-mic.txt new file mode 100644 index 00000000000..539adca19e8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/lpc32xx-mic.txt @@ -0,0 +1,38 @@ +* NXP LPC32xx Main Interrupt Controller + (MIC, including SIC1 and SIC2 secondary controllers) + +Required properties: +- compatible: Should be "nxp,lpc3220-mic" +- interrupt-controller: Identifies the node as an interrupt controller. +- interrupt-parent: Empty for the interrupt controller itself +- #interrupt-cells: The number of cells to define the interrupts. Should be 2. + The first cell is the IRQ number + The second cell is used to specify mode: + 1 = low-to-high edge triggered + 2 = high-to-low edge triggered + 4 = active high level-sensitive + 8 = active low level-sensitive + Default for internal sources should be set to 4 (active high). +- reg: Should contain MIC registers location and length + +Examples: + /* + * MIC + */ + mic: interrupt-controller@40008000 { + compatible = "nxp,lpc3220-mic"; + interrupt-controller; + interrupt-parent; + #interrupt-cells = <2>; + reg = <0x40008000 0xC000>; + }; + + /* + * ADC + */ + adc@40048000 { + compatible = "nxp,lpc3220-adc"; + reg = <0x40048000 0x1000>; + interrupt-parent = <&mic>; + interrupts = <39 4>; + }; diff --git a/Documentation/devicetree/bindings/arm/lpc32xx.txt b/Documentation/devicetree/bindings/arm/lpc32xx.txt new file mode 100644 index 00000000000..56ec8ddc4a3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/lpc32xx.txt @@ -0,0 +1,8 @@ +NXP LPC32xx Platforms Device Tree Bindings +------------------------------------------ + +Boards with the NXP LPC32xx SoC shall have the following properties: + +Required root node property: + +compatible: must be "nxp,lpc3220", "nxp,lpc3230", "nxp,lpc3240" or "nxp,lpc3250" |