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author | Ingo Molnar <mingo@kernel.org> | 2014-02-02 09:45:39 +0100 |
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committer | Ingo Molnar <mingo@kernel.org> | 2014-02-02 09:45:39 +0100 |
commit | eaa4e4fcf1b5c60e656d93242f7fe422173f25b2 (patch) | |
tree | c05d5d6ca3f625d72a9d136b4c485d3dc9472089 /Documentation/devicetree/bindings/clock/ti/apll.txt | |
parent | be1e4e760d940c14d119bffef5eb007dfdf29046 (diff) | |
parent | 5cb480f6b488128140c940abff3c36f524a334a8 (diff) |
Merge branch 'linus' into sched/core, to resolve conflicts
Conflicts:
kernel/sysctl.c
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/ti/apll.txt')
-rw-r--r-- | Documentation/devicetree/bindings/clock/ti/apll.txt | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/ti/apll.txt b/Documentation/devicetree/bindings/clock/ti/apll.txt new file mode 100644 index 00000000000..7faf5a68b3b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/apll.txt @@ -0,0 +1,31 @@ +Binding for Texas Instruments APLL clock. + +Binding status: Unstable - ABI compatibility may be broken in the future + +This binding uses the common clock binding[1]. It assumes a +register-mapped APLL with usually two selectable input clocks +(reference clock and bypass clock), with analog phase locked +loop logic for multiplying the input clock to a desired output +clock. This clock also typically supports different operation +modes (locked, low power stop etc.) APLL mostly behaves like +a subtype of a DPLL [2], although a simplified one at that. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/clock/ti/dpll.txt + +Required properties: +- compatible : shall be "ti,dra7-apll-clock" +- #clock-cells : from common clock binding; shall be set to 0. +- clocks : link phandles of parent clocks (clk-ref and clk-bypass) +- reg : address and length of the register set for controlling the APLL. + It contains the information of registers in the following order: + "control" - contains the control register base address + "idlest" - contains the idlest register base address + +Examples: + apll_pcie_ck: apll_pcie_ck@4a008200 { + #clock-cells = <0>; + clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; + reg = <0x4a00821c 0x4>, <0x4a008220 0x4>; + compatible = "ti,dra7-apll-clock"; + }; |