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authorLinus Torvalds <torvalds@linux-foundation.org>2012-12-11 11:30:41 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2012-12-11 11:30:41 -0800
commitb58ed041a360ed051fab17e4d9b0f451c6fedba7 (patch)
treec21db4bc5042821cae320213652b2dbec880a58d /Documentation/devicetree/bindings/i2c/i2c-pxa-pci-ce4100.txt
parent259cdbee2094d28b72f0f3d77bc9203d682994ff (diff)
parent58fea354d887fddddd342a8d14b02069161ca904 (diff)
Merge tag 'devicetree-for-linus' of git://git.secretlab.ca/git/linux-2.6
Pull device tree changes from Grant Likely: "Here are the DT changes I've got queued up for v3.8. As described below, there are a lot of bug fixes here and documentation updates but nothing major: Bug fixes, little cleanups, and documentation changes. The most invasive thing here touches a bunch of the arch directories to use a common build rule for .dtb files. There are no major changes to functionality here other than a few new helper functions." * tag 'devicetree-for-linus' of git://git.secretlab.ca/git/linux-2.6: (34 commits) arm64: Fix the dtbs target building mtd: nand: davinci: fix the binding documentation rtc: rtc-mv: Add the device tree binding documentation devicetree/bindings: Move gpio-leds binding into leds directory of/vendor-prefixes: add Imagination Technologies microblaze: use new common dtc rule c6x: use new common dtc rule openrisc: use new common dtc rule arm64: Add dtbs target for building all the enabled dtb files arm64: use new common dtc rule ARM: dt: change .dtb build rules to build in dts directory kbuild: centralize .dts->.dtb rule Fix build when CONFIG_W1_MASTER_GPIO=m b exporting "allnodes" of/spi: Honour "status=disabled" property of device of_mdio: Honour "status=disabled" property of device of_i2c: Honour "status=disabled" property of device powerpc: Fix fallout from device_node->name constification of: add 'const' for of_parse_phandle parameter *np Documentation: correct of_platform_populate() argument list script: dtc: clean generated files ...
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+CE4100 I2C
+----------
+
+CE4100 has one PCI device which is described as the I2C-Controller. This
+PCI device has three PCI-bars, each bar contains a complete I2C
+controller. So we have a total of three independent I2C-Controllers
+which share only an interrupt line.
+The driver is probed via the PCI-ID and is gathering the information of
+attached devices from the devices tree.
+Grant Likely recommended to use the ranges property to map the PCI-Bar
+number to its physical address and to use this to find the child nodes
+of the specific I2C controller. This were his exact words:
+
+ Here's where the magic happens. Each entry in
+ ranges describes how the parent pci address space
+ (middle group of 3) is translated to the local
+ address space (first group of 2) and the size of
+ each range (last cell). In this particular case,
+ the first cell of the local address is chosen to be
+ 1:1 mapped to the BARs, and the second is the
+ offset from be base of the BAR (which would be
+ non-zero if you had 2 or more devices mapped off
+ the same BAR)
+
+ ranges allows the address mapping to be described
+ in a way that the OS can interpret without
+ requiring custom device driver code.
+
+This is an example which is used on FalconFalls:
+------------------------------------------------
+ i2c-controller@b,2 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "pci8086,2e68.2",
+ "pci8086,2e68",
+ "pciclass,ff0000",
+ "pciclass,ff00";
+
+ reg = <0x15a00 0x0 0x0 0x0 0x0>;
+ interrupts = <16 1>;
+
+ /* as described by Grant, the first number in the group of
+ * three is the bar number followed by the 64bit bar address
+ * followed by size of the mapping. The bar address
+ * requires also a valid translation in parents ranges
+ * property.
+ */
+ ranges = <0 0 0x02000000 0 0xdffe0500 0x100
+ 1 0 0x02000000 0 0xdffe0600 0x100
+ 2 0 0x02000000 0 0xdffe0700 0x100>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ce4100-i2c-controller";
+
+ /* The first number in the reg property is the
+ * number of the bar
+ */
+ reg = <0 0 0x100>;
+
+ /* This I2C controller has no devices */
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ce4100-i2c-controller";
+ reg = <1 0 0x100>;
+
+ /* This I2C controller has one gpio controller */
+ gpio@26 {
+ #gpio-cells = <2>;
+ compatible = "ti,pcf8575";
+ reg = <0x26>;
+ gpio-controller;
+ };
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ce4100-i2c-controller";
+ reg = <2 0 0x100>;
+
+ gpio@26 {
+ #gpio-cells = <2>;
+ compatible = "ti,pcf8575";
+ reg = <0x26>;
+ gpio-controller;
+ };
+ };
+ };