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author | Mark Brown <broonie@linaro.org> | 2013-06-30 12:42:23 +0100 |
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committer | Mark Brown <broonie@linaro.org> | 2013-06-30 12:42:23 +0100 |
commit | 4494783793459dc601aad574802e81592cf3173f (patch) | |
tree | f0ca70f7b389c7a151c360f031a1dbb43a2cd110 /Documentation/devicetree/bindings/sound/adi,adau1701.txt | |
parent | f74b5e253a062004c1d30177f9889501423e403d (diff) | |
parent | cef929ec4e80fcfe249c800408a5f9d72ebd5933 (diff) |
Merge remote-tracking branch 'asoc/topic/adau1701' into asoc-next
Diffstat (limited to 'Documentation/devicetree/bindings/sound/adi,adau1701.txt')
-rw-r--r-- | Documentation/devicetree/bindings/sound/adi,adau1701.txt | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/sound/adi,adau1701.txt b/Documentation/devicetree/bindings/sound/adi,adau1701.txt new file mode 100644 index 00000000000..547a49b56a6 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/adi,adau1701.txt @@ -0,0 +1,35 @@ +Analog Devices ADAU1701 + +Required properties: + + - compatible: Should contain "adi,adau1701" + - reg: The i2c address. Value depends on the state of ADDR0 + and ADDR1, as wired in hardware. + +Optional properties: + + - reset-gpio: A GPIO spec to define which pin is connected to the + chip's !RESET pin. If specified, the driver will + assert a hardware reset at probe time. + - adi,pll-mode-gpios: An array of two GPIO specs to describe the GPIOs + the ADAU's PLL config pins are connected to. + The state of the pins are set according to the + configured clock divider on ASoC side before the + firmware is loaded. + - adi,pin-config: An array of 12 numerical values selecting one of the + pin configurations as described in the datasheet, + table 53. Note that the value of this property has + to be prefixed with '/bits/ 8'. + +Examples: + + i2c_bus { + adau1701@34 { + compatible = "adi,adau1701"; + reg = <0x34>; + reset-gpio = <&gpio 23 0>; + adi,pll-mode-gpios = <&gpio 24 0 &gpio 25 0>; + adi,pin-config = /bits/ 8 <0x4 0x7 0x5 0x5 0x4 0x4 + 0x4 0x4 0x4 0x4 0x4 0x4>; + }; + }; |