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authorSoren Brinkmann <soren.brinkmann@xilinx.com>2013-05-13 10:46:39 -0700
committerMichal Simek <michal.simek@xilinx.com>2013-05-27 09:21:49 +0200
commit97c4e87d45498fb4d18c995721bba72345a7d257 (patch)
tree424129bd5158d96ea5b3b68a02f7ef76170e5192 /Documentation/devicetree/bindings
parent30e1e28598c2674c133148d8aec6d431d7acd314 (diff)
clk: zynq: Remove deprecated clock code
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Rob Landley <rob@landley.net> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-doc@vger.kernel.org Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings')
-rw-r--r--Documentation/devicetree/bindings/clock/zynq-7000.txt48
1 files changed, 0 insertions, 48 deletions
diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt
index 1049a313933..d99af878f5d 100644
--- a/Documentation/devicetree/bindings/clock/zynq-7000.txt
+++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt
@@ -102,51 +102,3 @@ Example:
clocks = <&clkc 16>, <&clk_foo>;
clock-names = "gem1_emio_clk", "can_mio_clk_23";
};
-
-== PLLs ==
-
-Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.
-
-Required properties:
-- #clock-cells : shall be 0 (only one clock is output from this node)
-- compatible : "xlnx,zynq-pll"
-- reg : pair of u32 values, which are the address offsets within the SLCR
- of the relevant PLL_CTRL register and PLL_CFG register respectively
-- clocks : phandle for parent clock. should be the phandle for ps_clk
-
-Optional properties:
-- clock-output-names : name of the output clock
-
-Example:
- armpll: armpll {
- #clock-cells = <0>;
- compatible = "xlnx,zynq-pll";
- clocks = <&ps_clk>;
- reg = <0x100 0x110>;
- clock-output-names = "armpll";
- };
-
-== Peripheral clocks ==
-
-Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks.
-
-Required properties:
-- #clock-cells : shall be 1
-- compatible : "xlnx,zynq-periph-clock"
-- reg : a single u32 value, describing the offset within the SLCR where
- the CLK_CTRL register is found for this peripheral
-- clocks : phandle for parent clocks. should hold phandles for
- the IO_PLL, ARM_PLL, and DDR_PLL in order
-- clock-output-names : names of the output clock(s). For peripherals that have
- two output clocks (for example, the UART), two clocks
- should be listed.
-
-Example:
- uart_clk: uart_clk {
- #clock-cells = <1>;
- compatible = "xlnx,zynq-periph-clock";
- clocks = <&iopll &armpll &ddrpll>;
- reg = <0x154>;
- clock-output-names = "uart0_ref_clk",
- "uart1_ref_clk";
- };