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authorLinus Torvalds <torvalds@linux-foundation.org>2014-06-10 10:28:45 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2014-06-10 10:28:45 -0700
commit77c32bbbe0d0e963ba5723b8d1f6c42c5d56858b (patch)
tree2b819d3b7c00173c072fe61cadb0fd82ba51f417 /Documentation/devicetree
parentfad0701eaa091beb8ce5ef2eef04b5e833617368 (diff)
parent06822788faa21529a9a97965e266d77a596dc921 (diff)
Merge branch 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma
Pull slave-dmaengine updates from Vinod Koul: - new Xilixn VDMA driver from Srikanth - bunch of updates for edma driver by Thomas, Joel and Peter - fixes and updates on dw, ste_dma, freescale, mpc512x, sudmac etc * 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (45 commits) dmaengine: sh: don't use dynamic static allocation dmaengine: sh: fix print specifier warnings dmaengine: sh: make shdma_prep_dma_cyclic static dmaengine: Kconfig: Update MXS_DMA help text to include MX6Q/MX6DL of: dma: Grammar s/requests/request/, s/used required/required/ dmaengine: shdma: Enable driver compilation with COMPILE_TEST dmaengine: rcar-hpbdma: Include linux/err.h dmaengine: sudmac: Include linux/err.h dmaengine: sudmac: Keep #include sorted alphabetically dmaengine: shdmac: Include linux/err.h dmaengine: shdmac: Keep #include sorted alphabetically dmaengine: s3c24xx-dma: Add cyclic transfer support dmaengine: s3c24xx-dma: Process whole SG chain dmaengine: imx: correct sdmac->status for cyclic dma tx dmaengine: pch: fix compilation for alpha target dmaengine: dw: check return code of dma_async_device_register() dmaengine: dw: fix regression in dw_probe() function dmaengine: dw: enable clock before access dma: pch_dma: Fix Kconfig dependencies dmaengine: mpc512x: add support for peripheral transfers ...
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/dma/mmp-dma.txt11
-rw-r--r--Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt75
2 files changed, 82 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/dma/mmp-dma.txt b/Documentation/devicetree/bindings/dma/mmp-dma.txt
index a4fa4efa1d8..7a802f64e5b 100644
--- a/Documentation/devicetree/bindings/dma/mmp-dma.txt
+++ b/Documentation/devicetree/bindings/dma/mmp-dma.txt
@@ -1,17 +1,20 @@
* MARVELL MMP DMA controller
Marvell Peripheral DMA Controller
-Used platfroms: pxa688, pxa910, pxa3xx, etc
+Used platforms: pxa688, pxa910, pxa3xx, etc
Required properties:
- compatible: Should be "marvell,pdma-1.0"
- reg: Should contain DMA registers location and length.
- interrupts: Either contain all of the per-channel DMA interrupts
or one irq for pdma device
-- #dma-channels: Number of DMA channels supported by the controller.
+
+Optional properties:
+- #dma-channels: Number of DMA channels supported by the controller (defaults
+ to 32 when not specified)
"marvell,pdma-1.0"
-Used platfroms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
+Used platforms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
Examples:
@@ -45,7 +48,7 @@ pdma: dma-controller@d4000000 {
Marvell Two Channel DMA Controller used specifically for audio
-Used platfroms: pxa688, pxa910
+Used platforms: pxa688, pxa910
Required properties:
- compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ"
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
new file mode 100644
index 00000000000..1405ed071bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
@@ -0,0 +1,75 @@
+Xilinx AXI VDMA engine, it does transfers between memory and video devices.
+It can be configured to have one channel or two channels. If configured
+as two channels, one is to transmit to the video device and another is
+to receive from the video device.
+
+Required properties:
+- compatible: Should be "xlnx,axi-vdma-1.00.a"
+- #dma-cells: Should be <1>, see "dmas" property below
+- reg: Should contain VDMA registers location and length.
+- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
+- dma-channel child node: Should have at least one channel and can have up to
+ two channels per device. This node specifies the properties of each
+ DMA channel (see child node properties below).
+
+Optional properties:
+- xlnx,include-sg: Tells configured for Scatter-mode in
+ the hardware.
+- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
+ It takes following values:
+ {1}, flush both channels
+ {2}, flush mm2s channel
+ {3}, flush s2mm channel
+
+Required child node properties:
+- compatible: It should be either "xlnx,axi-vdma-mm2s-channel" or
+ "xlnx,axi-vdma-s2mm-channel".
+- interrupts: Should contain per channel VDMA interrupts.
+- xlnx,data-width: Should contain the stream data width, take values
+ {32,64...1024}.
+
+Optional child node properties:
+- xlnx,include-dre: Tells hardware is configured for Data
+ Realignment Engine.
+- xlnx,genlock-mode: Tells Genlock synchronization is
+ enabled/disabled in hardware.
+
+Example:
+++++++++
+
+axi_vdma_0: axivdma@40030000 {
+ compatible = "xlnx,axi-vdma-1.00.a";
+ #dma_cells = <1>;
+ reg = < 0x40030000 0x10000 >;
+ xlnx,num-fstores = <0x8>;
+ xlnx,flush-fsync = <0x1>;
+ dma-channel@40030000 {
+ compatible = "xlnx,axi-vdma-mm2s-channel";
+ interrupts = < 0 54 4 >;
+ xlnx,datawidth = <0x40>;
+ } ;
+ dma-channel@40030030 {
+ compatible = "xlnx,axi-vdma-s2mm-channel";
+ interrupts = < 0 53 4 >;
+ xlnx,datawidth = <0x40>;
+ } ;
+} ;
+
+
+* DMA client
+
+Required properties:
+- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
+ where Channel ID is '0' for write/tx and '1' for read/rx
+ channel.
+- dma-names: a list of DMA channel names, one per "dmas" entry
+
+Example:
+++++++++
+
+vdmatest_0: vdmatest@0 {
+ compatible ="xlnx,axi-vdma-test-1.00.a";
+ dmas = <&axi_vdma_0 0
+ &axi_vdma_0 1>;
+ dma-names = "vdma0", "vdma1";
+} ;