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authorHiroshi DOYU <hdoyu@nvidia.com>2012-05-10 10:45:32 +0300
committerJoerg Roedel <joerg.roedel@amd.com>2012-05-11 11:42:05 +0200
commit774dfc9bb7f2ab1950a790a8f13eca3d5c580033 (patch)
treec93680af050fcef7f5aff981ecfd3cf60abaf570 /Documentation
parent7cffae421e3cd29410ef4d75f2244655fdde3b60 (diff)
iommu/tegra: gart: Fix register offset correctly
DT passes the exact GART register ranges without any overlapping with MC register ranges. GART register offset needs to be adjusted by one passed by DT correctly. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt6
1 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt
index 2d87b9191fc..099d9362ebc 100644
--- a/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt
+++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt
@@ -7,8 +7,8 @@ Required properties:
Example:
- gart: gart@7000f000 {
+ gart {
compatible = "nvidia,tegra20-gart";
- reg = < 0x7000f000 0x00000100 /* controller registers */
- 0x58000000 0x02000000 >; /* GART aperture */
+ reg = <0x7000f024 0x00000018 /* controller registers */
+ 0x58000000 0x02000000>; /* GART aperture */
};