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authorDave Airlie <airlied@redhat.com>2014-04-05 16:13:08 +1000
committerDave Airlie <airlied@redhat.com>2014-04-05 16:13:08 +1000
commit82c68b6ccd54117a87cb2d9b91c2ee6e1280cf9d (patch)
treef7835f0e4a1884253cbd46bfdb7cbc4fa920b6cc /Documentation
parent243b930f8b228428c2a14ebbb09045041ed0bc70 (diff)
parentd105a6c97e43e35fd4f852928bb8a19df235c6e7 (diff)
Merge tag 'drm/tegra/for-3.15-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/tegra: Changes for v3.15-rc1 Implement eDP support for Tegra124 and support the PRIME vmap()/vunmap() operations. A symbol that is required for upcoming V4L2 support is now exported by the host1x driver. Relicense drivers under the GPL v2 for consistency. One exception is the public header file, which is relicensed under MIT to abide by the common rule. * tag 'drm/tegra/for-3.15-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: Use standard GPL v2 license text drm/tegra: Relicense under GPL v2 drm/tegra: Relicense public header under MIT drm/tegra: Add eDP support gpu: host1x: export host1x_syncpt_incr_max() function drm/tegra: prime: Add vmap support
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt42
1 files changed, 42 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
index efaeec8961b..efa8b8451f9 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
@@ -190,6 +190,48 @@ of the following host1x client modules:
- nvidia,edid: supplies a binary EDID blob
- nvidia,panel: phandle of a display panel
+- sor: serial output resource
+
+ Required properties:
+ - compatible: "nvidia,tegra124-sor"
+ - reg: Physical base address and length of the controller's registers.
+ - interrupts: The interrupt outputs from the controller.
+ - clocks: Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+ - clock-names: Must include the following entries:
+ - sor: clock input for the SOR hardware
+ - parent: input for the pixel clock
+ - dp: reference clock for the SOR clock
+ - safe: safe reference for the SOR clock during power up
+ - resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+ - reset-names: Must include the following entries:
+ - sor
+
+ Optional properties:
+ - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
+ - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
+ - nvidia,edid: supplies a binary EDID blob
+ - nvidia,panel: phandle of a display panel
+
+ Optional properties when driving an eDP output:
+ - nvidia,dpaux: phandle to a DispayPort AUX interface
+
+- dpaux: DisplayPort AUX interface
+ - compatible: "nvidia,tegra124-dpaux"
+ - reg: Physical base address and length of the controller's registers.
+ - interrupts: The interrupt outputs from the controller.
+ - clocks: Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+ - clock-names: Must include the following entries:
+ - dpaux: clock input for the DPAUX hardware
+ - parent: reference clock
+ - resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+ - reset-names: Must include the following entries:
+ - dpaux
+ - vdd-supply: phandle of a supply that powers the DisplayPort link
+
Example:
/ {