diff options
| author | H. Peter Anvin <hpa@linux.intel.com> | 2012-10-19 07:54:24 -0700 |
|---|---|---|
| committer | H. Peter Anvin <hpa@linux.intel.com> | 2012-10-19 07:55:09 -0700 |
| commit | 4533d86270d7986e00594495dde9a109d6be27ae (patch) | |
| tree | c2473cac653f7b98e5bd5e6475e63734be4b7644 /arch/arm/boot/dts/armada-370.dtsi | |
| parent | 21c5e50e15b1abd797e62f18fd7f90b9cc004cbd (diff) | |
| parent | 5bc66170dc486556a1e36fd384463536573f4b82 (diff) | |
Merge commit '5bc66170dc486556a1e36fd384463536573f4b82' into x86/urgent
From Borislav Petkov <bp@amd64.org>:
Below is a RAS fix which reverts the addition of a sysfs attribute
which we agreed is not needed, post-factum. And this should go in now
because that sysfs attribute is going to end up in 3.7 otherwise and
thus exposed to userspace; removing it then would be a lot harder.
This is done as a merge rather than a simple patch/cherry-pick since
the baseline for this patch was not in the previous x86/urgent.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/arm/boot/dts/armada-370.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/armada-370.dtsi | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 3228ccc8333..2069151afe0 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -21,6 +21,12 @@ model = "Marvell Armada 370 family SoC"; compatible = "marvell,armada370", "marvell,armada-370-xp"; + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + }; + mpic: interrupt-controller@d0020000 { reg = <0xd0020a00 0x1d0>, <0xd0021870 0x58>; @@ -31,5 +37,43 @@ compatible = "marvell,armada-370-xp-system-controller"; reg = <0xd0018200 0x100>; }; + + pinctrl { + compatible = "marvell,mv88f6710-pinctrl"; + reg = <0xd0018000 0x38>; + }; + + gpio0: gpio@d0018100 { + compatible = "marvell,orion-gpio"; + reg = <0xd0018100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; + }; + + gpio1: gpio@d0018140 { + compatible = "marvell,orion-gpio"; + reg = <0xd0018140 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; + }; + + gpio2: gpio@d0018180 { + compatible = "marvell,orion-gpio"; + reg = <0xd0018180 0x40>; + ngpios = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <91>; + }; }; }; |