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authorSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>2014-03-13 13:32:34 +0100
committerSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>2014-05-19 23:02:09 +0200
commit0bd4b3461b6d4d562520222cdb70bc826f7a225f (patch)
tree1867a7364be88c2ba415c5988066ca87857a98df /arch/arm/boot/dts/berlin2q.dtsi
parent55d3de54807943ac912456fbff2d4d3fba9d80ea (diff)
ARM: dts: berlin: add scu and chipctrl device nodes for BG2/BG2Q
This adds scu and general purpose registers device nodes required for SMP on Berlin BG2 and BG2Q SoCs. The secondary CPUs will pick their jump address from general purpose (SW generic) register 1. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Jisheng Zhang <jszhang@marvell.com> Tested-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/berlin2q.dtsi')
-rw-r--r--arch/arm/boot/dts/berlin2q.dtsi10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 07452a7483f..86d8a2c49f3 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -87,6 +87,11 @@
cache-level = <2>;
};
+ scu: snoop-control-unit@ad0000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0xad0000 0x58>;
+ };
+
local-timer@ad0600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xad0600 0x20>;
@@ -183,6 +188,11 @@
};
};
+ generic-regs@ea0110 {
+ compatible = "marvell,berlin-generic-regs", "syscon";
+ reg = <0xea0110 0x10>;
+ };
+
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;