diff options
| author | Jisheng Zhang <jszhang@marvell.com> | 2014-06-12 17:38:40 +0800 |
|---|---|---|
| committer | Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | 2014-06-16 13:09:04 +0200 |
| commit | 44991eb4bfd63b043b50e880d347a7946d6a9736 (patch) | |
| tree | 8fcacf5483a5efe8b605521867cdbc72fc1c3ede /arch/arm/boot/dts/berlin2q.dtsi | |
| parent | 7171511eaec5bf23fb06078f59784a3a0626b38f (diff) | |
ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles
For all BG2Q SoCs, 2 cycles is the best/correct value.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/berlin2q.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/berlin2q.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 635a16a64cb..3f95dc568b2 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -90,6 +90,8 @@ compatible = "arm,pl310-cache"; reg = <0xac0000 0x1000>; cache-level = <2>; + arm,data-latency = <2 2 2>; + arm,tag-latency = <2 2 2>; }; scu: snoop-control-unit@ad0000 { |