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authorMinal Shah <minalkshah@gmail.com>2014-05-19 14:45:47 +0530
committerTony Lindgren <tony@atomide.com>2014-05-19 17:20:31 -0700
commitff66a3c86e004ce83f7c6e5f459d65c87f9d02b6 (patch)
tree5eef6e8cfd9ebd9f8657b51ccd0eb26f1968fe6d /arch/arm/boot/dts/dra7.dtsi
parent7b25babf6ebd3f9b182f3c78021f4dc87d77ed85 (diff)
ARM: dts: dra7: add support for parallel NAND flash
DRA7xx platform has in-build GPMC and ELM h/w engines which can be used for accessing externel NAND flash device. This patch: - adds generic DT binding in dra7.dtsi for enabling GPMC and ELM h/w engines - adds DT binding for Micron NAND Flash (MT29F2G16AADWP) present on dra7-evm *Important* On DRA7 EVM, GPMC_WPN and NAND_BOOTn are controlled by DIP switch So following board settings are required for NAND device detection: SW5.9 (GPMC_WPN) = LOW SW5.1 (NAND_BOOTn) = HIGH Signed-off-by: Minal Shah <minalkshah@gmail.com> Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dra7.dtsi')
-rw-r--r--arch/arm/boot/dts/dra7.dtsi20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 6af8b080ea6..a8a0ceec677 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -964,6 +964,26 @@
dr_mode = "otg";
};
};
+
+ elm: elm@48078000 {
+ compatible = "ti,am3352-elm";
+ reg = <0x48078000 0xfc0>; /* device IO registers */
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "elm";
+ status = "disabled";
+ };
+
+ gpmc: gpmc@50000000 {
+ compatible = "ti,am3352-gpmc";
+ ti,hwmods = "gpmc";
+ reg = <0x50000000 0x37c>; /* device IO registers */
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ gpmc,num-cs = <8>;
+ gpmc,num-waitpins = <2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ status = "disabled";
+ };
};
};