diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2013-06-20 02:11:29 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2013-06-20 02:11:29 +0200 |
| commit | ed2ca6ee4bfd060c079fd05d0eb8862da02dd248 (patch) | |
| tree | f395e9fd07353c4070f18a0b1d1d29c220ee8114 /arch/arm/boot/dts/imx6q.dtsi | |
| parent | f25a4d68f8ca83132dcfb8607d55fc71b12956c0 (diff) | |
| parent | 93b331cec9e15210af1da9782bf699e5d3a61f0f (diff) | |
Merge tag 'imx-dt-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt
From Shawn Guo:
imx device tree changes for 3.11:
* A bunch of new board additions, imx6sl-evk, vf610-twr, imx53-tx53,
imx53-m53evk and imx27-phytec-phycore
* Various pinctrl setting updates and additions
* Enable various on board peripherals, usb, audio, nor, display etc.
* Configure L2 cache data and tag latency from device tree
* Add imx-weim bus driver
* tag 'imx-dt-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6: (82 commits)
ARM: dts: imx27: Add VPU devicetree node
ARM: mxc: fix gpio-ranges for VF610
ARM: dtsi: imx6qdl-sabresd: Enable WM8962 audio support
ARM: dtsi: imx6qdl-sabresd: Enable SSI2 and AUDMUX
ARM: dtsi: imx6qdl-sabresd: Add WM8962 CODEC support
ARM: dtsi: imx6qdl-sabresd: add a fixed regulator for WM8962
ARM: dtsi: imx6dl: Add a pinctrl for AUDMUX
ARM: dtsi: imx6q/imx6dl: Add a pinctrl for I2C1
ARM: dts: imx6qdl-sabresd: add clko1 iomux configuration
ARM: dts: Phytec imx6q pfla02 and pbab01 support
ARM: dts: imx6q: Add pinctrl for usdhc2 and enet
ARM: dts: imx27-phytec-phycore-rdk: Add MTD name for NOR flash
ARM: dts: imx27-phytec-phycore-rdk: Add SDHC support
ARM: dts: i.MX27: Add SDHC devicetree nodes
ARM: dts: i.MX27: Add DMA devicetree node
ARM: dts: imx6qdl-sabreauto: enable the WEIM NOR
ARM: dts: imx6dl: add pinctrls for WEIM NOR
ARM: dts: imx6q: add pinctrls for WEIM NOR
ARM: dts: imx6qdl: add more information for WEIM
ARM: dts: imx6q{dl}: fix the pin conflict between SPI and WEIM
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot/dts/imx6q.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6q.dtsi | 100 |
1 files changed, 98 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index dc54a72a3bc..ba09dc32324 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -161,6 +161,27 @@ MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 >; }; + + pinctrl_enet_3: enetgrp-3 { + fsl,pins = < + MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + >; + }; }; gpmi-nand { @@ -172,8 +193,6 @@ MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000 MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1 - MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1 MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1 MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1 MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1 @@ -196,6 +215,13 @@ MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 >; }; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; }; i2c2 { @@ -272,6 +298,17 @@ MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059 >; }; + + pinctrl_usdhc2_2: usdhc2grp-2 { + fsl,pins = < + MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; }; usdhc3 { @@ -329,6 +366,65 @@ >; }; }; + + weim { + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX6Q_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor_1: weimnorgrp-1 { + fsl,pins = < + MX6Q_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6Q_PAD_EIM_RW__EIM_RW 0xb0b1 + MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 + /* data */ + MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0 + MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0 + MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0 + MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0 + MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0 + MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0 + MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0 + MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0 + MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0 + MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0 + MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0 + MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0 + MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0 + MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0 + MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0 + MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0 + /* address */ + MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1 + MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1 + MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1 + MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1 + MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1 + MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1 + MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1 + MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1 + MX6Q_PAD_EIM_DA15__EIM_AD15 0xb0b1 + MX6Q_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6Q_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6Q_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6Q_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6Q_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6Q_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6Q_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6Q_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6Q_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6Q_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6Q_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6Q_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6Q_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6Q_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6Q_PAD_EIM_DA0__EIM_AD00 0xb0b1 + >; + }; + + }; }; }; |