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authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>2013-05-15 15:36:56 +0200
committerJason Cooper <jason@lakedaemon.net>2013-05-27 16:02:11 +0000
commit670ee03ccc29b3a14c6cbe04241c903342442c23 (patch)
tree8f344458b708fa4174a533594a150e0a60b91b98 /arch/arm/boot/dts/kirkwood-6281.dtsi
parent5afb9fe3678e2f54ba455a4c8b0c640037ca4775 (diff)
arm: kirkwood: add SoC-level Device Tree data for PCIe interfaces
This commit adds Device Tree details to enable the PCIe interfaces on Kirkwood. The 6281 has one PCIe interface, the 6282 has two PCIe interfaces. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/boot/dts/kirkwood-6281.dtsi')
-rw-r--r--arch/arm/boot/dts/kirkwood-6281.dtsi31
1 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
index d6c9d65cbae..51376683dbc 100644
--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -40,5 +40,36 @@
marvell,function = "sdio";
};
};
+
+ pcie-controller {
+ compatible = "marvell,kirkwood-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */
+ 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
+ 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
+
+ pcie@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &intc 9>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gate_clk 2>;
+ status = "disabled";
+ };
+ };
};
};