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authorArnd Bergmann <arnd@arndb.de>2014-02-25 18:09:27 +0100
committerArnd Bergmann <arnd@arndb.de>2014-02-25 18:09:27 +0100
commitf1a0d58e876be28bd2f53b55dd20d3cba92c6937 (patch)
tree3be5116e2de217634ca3f99fe2459ac8a39025be /arch/arm/boot/dts/qcom-msm8660-surf.dts
parenta3f4fdf2190edef9d0d7a9bd6246e7f599284590 (diff)
parentcf1e8f0cd665e2a9966d2bee4e11ecc0938ff166 (diff)
Merge branch 'qcom/cleanup' into next/drivers
* qcom/cleanup: ARM: qcom: Rename various msm prefixed functions to qcom clocksource: qcom: split building of legacy vs multiplatform support ARM: qcom: Split Qualcomm support into legacy and multiplatform clocksource: qcom: Move clocksource code out of mach-msm ARM: msm: kill off hotplug.c ARM: msm: Remove pen_release usage ARM: dts: msm: split out msm8660 and msm8960 soc into dts include This cleanup branch is a dependency for the following qcom driver changes. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot/dts/qcom-msm8660-surf.dts')
-rw-r--r--arch/arm/boot/dts/qcom-msm8660-surf.dts59
1 files changed, 1 insertions, 58 deletions
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts
index 68a72f5507b..169bad90dac 100644
--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
@@ -1,63 +1,6 @@
-/dts-v1/;
-
-/include/ "skeleton.dtsi"
-
-#include <dt-bindings/clock/qcom,gcc-msm8660.h>
+#include "qcom-msm8660.dtsi"
/ {
model = "Qualcomm MSM8660 SURF";
compatible = "qcom,msm8660-surf", "qcom,msm8660";
- interrupt-parent = <&intc>;
-
- intc: interrupt-controller@2080000 {
- compatible = "qcom,msm-8660-qgic";
- interrupt-controller;
- #interrupt-cells = <3>;
- reg = < 0x02080000 0x1000 >,
- < 0x02081000 0x1000 >;
- };
-
- timer@2000000 {
- compatible = "qcom,scss-timer", "qcom,msm-timer";
- interrupts = <1 0 0x301>,
- <1 1 0x301>,
- <1 2 0x301>;
- reg = <0x02000000 0x100>;
- clock-frequency = <27000000>,
- <32768>;
- cpu-offset = <0x40000>;
- };
-
- msmgpio: gpio@800000 {
- compatible = "qcom,msm-gpio";
- reg = <0x00800000 0x4000>;
- gpio-controller;
- #gpio-cells = <2>;
- ngpio = <173>;
- interrupts = <0 16 0x4>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gcc: clock-controller@900000 {
- compatible = "qcom,gcc-msm8660";
- #clock-cells = <1>;
- #reset-cells = <1>;
- reg = <0x900000 0x4000>;
- };
-
- serial@19c40000 {
- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
- reg = <0x19c40000 0x1000>,
- <0x19c00000 0x1000>;
- interrupts = <0 195 0x0>;
- clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
- clock-names = "core", "iface";
- };
-
- qcom,ssbi@500000 {
- compatible = "qcom,ssbi";
- reg = <0x500000 0x1000>;
- qcom,controller-type = "pmic-arbiter";
- };
};