diff options
| author | Stephen Warren <swarren@nvidia.com> | 2012-09-19 12:02:31 -0600 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2012-11-16 12:22:16 -0700 |
| commit | 2f2b7fb202a2fa93702a79d36033e5c8bee0120d (patch) | |
| tree | 22d29b27f152fc0b9a87f1d80ff57dcbaa65b59d /arch/arm/boot/dts/tegra20.dtsi | |
| parent | 9a2ab3f1fa01a146a395197153af0ae586e6a682 (diff) | |
ARM: tegra: define DT bindings for and instantiate timer
The Tegra timer provides a number of 29-bit timer channels, a single
32-bit free running counter, and in the Tegra30 variant, 5 watchdog modules.
The first two channels may also trigger a legacy watchdog reset.
Define a DT binding for this HW module, and add the module into the Tegra
device tree files.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra20.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index fba998e3954..96c922d8bb3 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -108,6 +108,15 @@ #interrupt-cells = <3>; }; + timer@60005000 { + compatible = "nvidia,tegra20-timer"; + reg = <0x60005000 0x60>; + interrupts = <0 0 0x04 + 0 1 0x04 + 0 41 0x04 + 0 42 0x04>; + }; + apbdma: dma { compatible = "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1200>; |