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authorLucas Stach <dev@lynxeye.de>2013-01-22 22:46:07 +0100
committerStephen Warren <swarren@nvidia.com>2013-01-28 11:24:09 -0700
commitab343e91aa00d6cc1047e8209d610c384ee824b9 (patch)
treed8e4ba8a829d4c1b6922ac511de9df27521ccb22 /arch/arm/boot/dts/tegra20.dtsi
parentc0967ce0a7388fa8818f5529897140f4f7ec8543 (diff)
ARM: tegra: move serial clock-frequency attr into the Tegra20 dtsi
No Tegra20 Platform is running PLL_P at another rate than 216MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 47534d9970b..63b0d81dc66 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -247,6 +247,7 @@
reg = <0x70006000 0x40>;
reg-shift = <2>;
interrupts = <0 36 0x04>;
+ clock-frequency = <216000000>;
nvidia,dma-request-selector = <&apbdma 8>;
clocks = <&tegra_car 6>;
status = "disabled";
@@ -257,6 +258,7 @@
reg = <0x70006040 0x40>;
reg-shift = <2>;
interrupts = <0 37 0x04>;
+ clock-frequency = <216000000>;
nvidia,dma-request-selector = <&apbdma 9>;
clocks = <&tegra_car 96>;
status = "disabled";
@@ -267,6 +269,7 @@
reg = <0x70006200 0x100>;
reg-shift = <2>;
interrupts = <0 46 0x04>;
+ clock-frequency = <216000000>;
nvidia,dma-request-selector = <&apbdma 10>;
clocks = <&tegra_car 55>;
status = "disabled";
@@ -277,6 +280,7 @@
reg = <0x70006300 0x100>;
reg-shift = <2>;
interrupts = <0 90 0x04>;
+ clock-frequency = <216000000>;
nvidia,dma-request-selector = <&apbdma 19>;
clocks = <&tegra_car 65>;
status = "disabled";
@@ -287,6 +291,7 @@
reg = <0x70006400 0x100>;
reg-shift = <2>;
interrupts = <0 91 0x04>;
+ clock-frequency = <216000000>;
nvidia,dma-request-selector = <&apbdma 20>;
clocks = <&tegra_car 66>;
status = "disabled";