diff options
| author | Stephen Warren <swarren@nvidia.com> | 2013-01-23 09:43:49 -0700 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-01-28 11:24:09 -0700 |
| commit | abf80c276dca1bf40b342b4ebf7815be0f6ba564 (patch) | |
| tree | 4b90282b64e4f0b74200c120c96206c052dd6dfa /arch/arm/boot/dts/tegra30-cardhu.dtsi | |
| parent | bf5fcc76d31418950b214542440d5de6e48c7998 (diff) | |
ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi
No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is
any using any other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra30-cardhu.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index ff6b68fe08a..17499272a4e 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -120,13 +120,11 @@ serial@70006000 { status = "okay"; - clock-frequency = <408000000>; }; serial@70006200 { compatible = "nvidia,tegra30-hsuart"; status = "okay"; - clock-frequency = <408000000>; }; i2c@7000c000 { |