diff options
| author | Barry Song <Baohua.Song@csr.com> | 2011-09-15 19:16:28 -0700 |
|---|---|---|
| committer | Barry Song <Barry.Song@csr.com> | 2011-10-24 02:54:21 -0700 |
| commit | 917d853564530dd5e73c8c1604e823465ff9b713 (patch) | |
| tree | a3163bda42777b827d0678cd3d02d69ec811d63f /arch/arm/boot/dts | |
| parent | 1e11bec9b09a28f81dd3173fec6b1c6c56b5e299 (diff) | |
ARM: CSR: call l2x0_of_init to init L2 cache of SiRFprimaII
Cc: Rob Herring <robherring2@gmail.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Diffstat (limited to 'arch/arm/boot/dts')
| -rw-r--r-- | arch/arm/boot/dts/prima2-cb.dts | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts index 17b6737c4ee..34ae3a64ba2 100644 --- a/arch/arm/boot/dts/prima2-cb.dts +++ b/arch/arm/boot/dts/prima2-cb.dts @@ -39,9 +39,12 @@ ranges = <0x40000000 0x40000000 0x80000000>; l2-cache-controller@80040000 { - compatible = "arm,pl310-cache"; + compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; reg = <0x80040000 0x1000>; interrupts = <59>; + arm,tag-latency = <1 1 1>; + arm,data-latency = <1 1 1>; + arm,filter-ranges = <0 0x40000000>; }; intc: interrupt-controller@80020000 { |