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authorThierry Reding <treding@nvidia.com>2014-07-18 12:11:03 +0200
committerThierry Reding <treding@nvidia.com>2014-12-04 16:16:13 +0100
commitc6f70a4d175bcecd56e0ba541ecf6905b4fb80fe (patch)
tree3ba09b85f650aaf15ca5c79f0a8f8f590f903ab8 /arch/arm/boot/dts
parenta9fe468f1b7d369467fffc8357577d2ffb4e73fd (diff)
ARM: tegra: Add memory controller support for Tegra114
Add the device tree node for the memory controller found on Tegra114 SoCs. The memory controller integrates an IOMMU (called SMMU) as well as various knobs to tweak memory accesses by the various clients. The old IOMMU device tree node is collapsed into the memory controller node to more accurately describe the hardware. While this change is incompatible, the IOMMU driver has never had any users so the change is not going to cause any breakage. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi18
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 2ca9c1807f7..2c26b07c11e 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -505,15 +505,15 @@
reset-names = "fuse";
};
- iommu@70019010 {
- compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
- reg = <0x70019010 0x02c
- 0x700191f0 0x010
- 0x70019228 0x074>;
- nvidia,#asids = <4>;
- dma-window = <0 0x40000000>;
- nvidia,swgroups = <0x18659fe>;
- nvidia,ahb = <&ahb>;
+ mc: memory-controller@70019000 {
+ compatible = "nvidia,tegra114-mc";
+ reg = <0x70019000 0x1000>;
+ clocks = <&tegra_car TEGRA114_CLK_MC>;
+ clock-names = "mc";
+
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+
+ #iommu-cells = <1>;
};
ahub@70080000 {