diff options
author | Stephen Warren <swarren@nvidia.com> | 2013-01-28 11:22:46 -0700 |
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committer | Stephen Warren <swarren@nvidia.com> | 2013-01-28 11:22:46 -0700 |
commit | ee059485175b21079d3639f167980d354afb3d4b (patch) | |
tree | 30bf32ec57ba915d31348c1b603481baf42c81dd /arch/arm/boot | |
parent | 1d328606c66b9bb1c0552f585943d596f37ae3b9 (diff) | |
parent | 80d9375617f7544f7475e7f07003a08930559d43 (diff) |
Merge branch 'for-3.9/scu-base-rework' into for-3.9/soc-t114
Conflicts:
arch/arm/mach-tegra/platsmp.c
Diffstat (limited to 'arch/arm/boot')
-rw-r--r-- | arch/arm/boot/dts/tegra20.dtsi | 17 | ||||
-rw-r--r-- | arch/arm/boot/dts/tegra30.dtsi | 29 |
2 files changed, 46 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 64939157987..2e7c83c7253 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -489,6 +489,23 @@ status = "disabled"; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <0 56 0x04 diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index b1483d92587..2de8b919d78 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -506,6 +506,35 @@ status = "disabled"; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + }; + }; + pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <0 144 0x04 |