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authorWill Deacon <will.deacon@arm.com>2011-11-25 19:23:36 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-11-26 21:58:55 +0000
commitfe41db7b3aca512e19b8ef4fbd5ad55545005d25 (patch)
treec48f6e939edb9140484d511c42dba65487dc92b2 /arch/arm/common/gic.c
parentabdd7b91dab2f8b2e32e90e4b7e809ffb462a662 (diff)
ARM: 7177/1: GIC: avoid skipping non-existent PPIs in irq_start calculation
Commit 4294f8baa ("ARM: gic: add irq_domain support") defines irq_start as irq_start = (irq_start & ~31) + 16; On a platform with a GIC and a CPU without PPIs, this results in irq_start being off by 16. This patch fixes gic_init so that we only carve out a PPI space when PPIs exist for the GIC being initialised. Cc: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/common/gic.c')
-rw-r--r--arch/arm/common/gic.c13
1 files changed, 8 insertions, 5 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 43240f315de..410a546060a 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -582,13 +582,16 @@ void __init gic_init(unsigned int gic_nr, int irq_start,
* For primary GICs, skip over SGIs.
* For secondary GICs, skip over PPIs, too.
*/
+ domain->hwirq_base = 32;
if (gic_nr == 0) {
gic_cpu_base_addr = cpu_base;
- domain->hwirq_base = 16;
- if (irq_start > 0)
- irq_start = (irq_start & ~31) + 16;
- } else
- domain->hwirq_base = 32;
+
+ if ((irq_start & 31) > 0) {
+ domain->hwirq_base = 16;
+ if (irq_start != -1)
+ irq_start = (irq_start & ~31) + 16;
+ }
+ }
/*
* Find out how many interrupts are supported.