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| author | Robert Richter <robert.richter@amd.com> | 2010-10-06 12:27:53 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2010-10-20 04:42:13 +0200 |
| commit | a68c439b1966c91f0ef474e2bf275d6792312726 (patch) | |
| tree | 9a49f060ee7d20a23fa8d3990e7f733aef60b15c /arch/arm/common/via82c505.c | |
| parent | 14d4962dc863ab42e898d66d4837aa6c3afedc3b (diff) | |
apic, x86: Check if EILVT APIC registers are available (AMD only)
This patch implements checks for the availability of LVT entries
(APIC500-530) and reserves it if used. The check becomes
necessary since we want to let the BIOS provide the LVT offsets.
The offsets should be determined by the subsystems using it
like those for MCE threshold or IBS. On K8 only offset 0
(APIC500) and MCE interrupts are supported. Beginning with
family 10h at least 4 offsets are available.
Since offsets must be consistent for all cores, we keep track of
the LVT offsets in software and reserve the offset for the same
vector also to be used on other cores. An offset is freed by
setting the entry to APIC_EILVT_MASKED.
If the BIOS is right, there should be no conflicts. Otherwise a
"[Firmware Bug]: ..." error message is generated. However, if
software does not properly determines the offsets, it is not
necessarily a BIOS bug.
Signed-off-by: Robert Richter <robert.richter@amd.com>
LKML-Reference: <1286360874-1471-2-git-send-email-robert.richter@amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/arm/common/via82c505.c')
0 files changed, 0 insertions, 0 deletions