diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2012-01-07 12:44:37 +0000 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2012-01-07 20:40:51 +0000 |
| commit | b001befe58691ef3627458cd814e8cee7f845c5f (patch) | |
| tree | 1083f1a1cd3feeceeac4b395534df0ff032fdbc8 /arch/arm/include/asm/hardware/entry-macro-gic.S | |
| parent | 31b2a868451d630bacfdeddc626371b3f9d9a01c (diff) | |
| parent | 928a11ba36f999436915ea2b1eadf54301f93059 (diff) | |
Merge branch 'samsung/dt' into next/dt
* samsung/dt: (3 commit)
Merge branch 'depends/rmk/for-linus' into samsung/dt
Merge branch 'depends/rmk/restart' into next/cleanup
Merge branch 'next/cleanup' into samsung/dt
Conflicts:
arch/arm/mach-tegra/board-dt.c
arch/arm/mach-tegra/include/mach/entry-macro.S
The latest version of the samsung/dt branch resolves
all sorts of conflicts with the latest upstream, no functional
changes that are not already there.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/include/asm/hardware/entry-macro-gic.S')
| -rw-r--r-- | arch/arm/include/asm/hardware/entry-macro-gic.S | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S deleted file mode 100644 index 74ebc803904..00000000000 --- a/arch/arm/include/asm/hardware/entry-macro-gic.S +++ /dev/null @@ -1,60 +0,0 @@ -/* - * arch/arm/include/asm/hardware/entry-macro-gic.S - * - * Low-level IRQ helper macros for GIC - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <asm/hardware/gic.h> - -#ifndef HAVE_GET_IRQNR_PREAMBLE - .macro get_irqnr_preamble, base, tmp - ldr \base, =gic_cpu_base_addr - ldr \base, [\base] - .endm -#endif - -/* - * The interrupt numbering scheme is defined in the - * interrupt controller spec. To wit: - * - * Interrupts 0-15 are IPI - * 16-31 are local. We allow 30 to be used for the watchdog. - * 32-1020 are global - * 1021-1022 are reserved - * 1023 is "spurious" (no interrupt) - * - * A simple read from the controller will tell us the number of the highest - * priority enabled interrupt. We then just need to check whether it is in the - * valid range for an IRQ (30-1020 inclusive). - */ - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - ldr \irqstat, [\base, #GIC_CPU_INTACK] - /* bits 12-10 = src CPU, 9-0 = int # */ - - ldr \tmp, =1021 - bic \irqnr, \irqstat, #0x1c00 - cmp \irqnr, #15 - cmpcc \irqnr, \irqnr - cmpne \irqnr, \tmp - cmpcs \irqnr, \irqnr - .endm - -/* We assume that irqstat (the raw value of the IRQ acknowledge - * register) is preserved from the macro above. - * If there is an IPI, we immediately signal end of interrupt on the - * controller, since this requires the original irqstat value which - * we won't easily be able to recreate later. - */ - - .macro test_for_ipi, irqnr, irqstat, base, tmp - bic \irqnr, \irqstat, #0x1c00 - cmp \irqnr, #16 - strcc \irqstat, [\base, #GIC_CPU_EOI] - cmpcs \irqnr, \irqnr - .endm |