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authorWill Deacon <will.deacon@arm.com>2010-11-25 12:01:54 +0000
committerWill Deacon <will.deacon@arm.com>2010-12-06 11:55:56 +0000
commit6ee33c2712fcdff2568d9bbadb25c8e5a7c36212 (patch)
tree94c2510ccdd1cb2843897422746b67adf6ba1cd5 /arch/arm/kernel/entry-armv.S
parent7d99331e4793b52d488e911876ef11d843c6c8c9 (diff)
ARM: hw_breakpoint: correct and simplify alignment fixup code
The current hw_breakpoint code tries to fix up the alignment of breakpoints so that we can make use of sparse byte-address-select bits in the control register and give the illusion that we can set breakpoints on unaligned addresses. Although this works on v6 cores, v7 forbids this behaviour, instead requiring breakpoints to be set on aligned addresses and have contiguous byte-address-select ranges depending on the instruction set in use. For ARM the only supported size is 4 bytes, whilst Thumb-2 also permits 2 byte breakpoints (watchpoints can be of 1, 2, 4 or 8 bytes long). This patch simplifies the alignment fixup code so that we require addresses to be aligned to the size of the corresponding breakpoint. This allows us to handle the common case of breaking on a half-word aligned Thumb-2 instruction and also allows us to set byte watchpoints on arbitrary addresses. Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/kernel/entry-armv.S')
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