diff options
| author | Jon Medhurst <tixy@yxit.co.uk> | 2011-06-16 14:53:56 +0100 |
|---|---|---|
| committer | Tixy <tixy@medhuaa1.miniserver.com> | 2011-07-13 17:32:42 +0000 |
| commit | 6aaa8b5570c7b5b9eb8913ec80263a1012b1dd66 (patch) | |
| tree | 45a54e0b4f25b7e6979d16870f3d23fdd28b3a78 /arch/arm/kernel/kprobes.h | |
| parent | eaf4f33feca2704ad1d06f1ef6b427712c506cc0 (diff) | |
ARM: kprobes: Add it_advance()
This advances the ITSTATE bits in CPSR to their values for the next
instruction.
Signed-off-by: Jon Medhurst <tixy@yxit.co.uk>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Diffstat (limited to 'arch/arm/kernel/kprobes.h')
| -rw-r--r-- | arch/arm/kernel/kprobes.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/kernel/kprobes.h b/arch/arm/kernel/kprobes.h index a84b14d8cdc..5e2485c4cac 100644 --- a/arch/arm/kernel/kprobes.h +++ b/arch/arm/kernel/kprobes.h @@ -69,6 +69,31 @@ void __init find_str_pc_offset(void); /* + * Update ITSTATE after normal execution of an IT block instruction. + * + * The 8 IT state bits are split into two parts in CPSR: + * ITSTATE<1:0> are in CPSR<26:25> + * ITSTATE<7:2> are in CPSR<15:10> + */ +static inline unsigned long it_advance(unsigned long cpsr) + { + if ((cpsr & 0x06000400) == 0) { + /* ITSTATE<2:0> == 0 means end of IT block, so clear IT state */ + cpsr &= ~PSR_IT_MASK; + } else { + /* We need to shift left ITSTATE<4:0> */ + const unsigned long mask = 0x06001c00; /* Mask ITSTATE<4:0> */ + unsigned long it = cpsr & mask; + it <<= 1; + it |= it >> (27 - 10); /* Carry ITSTATE<2> to correct place */ + it &= mask; + cpsr &= ~mask; + cpsr |= it; + } + return cpsr; +} + +/* * Test if load/store instructions writeback the address register. * if P (bit 24) == 0 or W (bit 21) == 1 */ |