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authorWill Deacon <will.deacon@arm.com>2010-02-26 10:46:15 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-03-13 10:50:29 +0000
commitd10fca9f39238b07cc670b441d2b423de30359d2 (patch)
treed5b988628ad269d4d3f39b76ec55d9855a223988 /arch/arm/kernel/perf_event.c
parentddee87f208b6229d2910dd5930c87089dc56c87e (diff)
ARM: 5960/1: ARM: perf-events: fix v7 event selection mask
The event selection mask for ARMv7 cores [ARMV7_EVTSEL_MASK] is incorrectly set to 0x7f. This means that the top bit of an event ID is ignored, so counting branch misses (id=0x10) and ISBs (id=0x90) give the same results. This patch sets the event selection mask to the correct value of 0xff. Signed-off-by: Jean Pihet <jpihet@mvista.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/kernel/perf_event.c')
-rw-r--r--arch/arm/kernel/perf_event.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index b44d15948b5..c45a155a73d 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -1625,7 +1625,7 @@ enum armv7_counters {
/*
* EVTSEL: Event selection reg
*/
-#define ARMV7_EVTSEL_MASK 0x7f /* Mask for writable bits */
+#define ARMV7_EVTSEL_MASK 0xff /* Mask for writable bits */
/*
* SELECT: Counter selection reg